A simplified bi-directional shift register and a single-latch circuit for implementing the bi-directional shift register thereof which obviates the use of a conventional dual-latch (i.e., master/slave) configuration in the bi-directional shift register design is described. The single-latch circuit includes an input circuit portion and a latching circuit portion. The input circuit portion receives input signals including the output data from previous and next single-latch circuits in the shift register and right shift and left shift control signals. Dependent on the input signals, the input circuit portion drives an input node coupled to the latching circuit portion with a data value to be shifted which corresponds to data from one of the previous and next single-latch circuits. The latching circuit portion includes a tri-state inverter which is responsive to the system clock signal such that when the clock signal transitions to a given state, the data value to be shifted is latched to the output of the single-latch circuit wherein the shift operation is performed. A delay lock loop circuit implemented with a bi-directional shift register designed with the single-latch circuit has reduced size and minimized noise due to the simplicity of the single-latch circuit.
A master-slave flip-flop circuit (200, 200') includes a master latch circuit (202) and slave latch circuit (203). A hold control component (220) included in the master latch circuit (202) is interposed between a master latch node (ML) and a slave input node (SI). The hold control component blocks the transfer of data from the master latch node (ML) to the slave input node (SI) in response to a hold input. In the preferred form of the invention of the hold control component (220) comprises a tri-state inverter having an input connected to the master latch node (ML) and an output connected to the slave input node (SI). The hold input, comprising a high level hold signal and its complementary or inverted signal, disables the tri-state inverter and thus prevent data from being transferred from the master latch node (ML) to the slave input node (SI). When the hold input is removed, that is, when the hold signal is at a low logical level and complementary signal is at a high logical level, the master-slave flip-flop circuit (200, 200') operates in the normal fashion, receiving and latching new data in each clock cycle and applying that new data to the circuit output.
Delay lock loop (DLL) circuits, systems, and methods providing glitch-free output clock signals. Glitches are eliminated from an output clock signal by using shift registers including a single token bit to select one of many delayed clock signals. A DLL clock multiplexer includes a series of shift registers, each of which selects only one of the many input clock signals at each stage. Thus, only one clock signal is selected at any given time. Delay is added or subtracted from the loop by shifting the token bit within each shift register. The token bit is shifted by a single position at a time. Therefore, no glitching occurs.
The present invention provides a register controlled delay locked loop (DLL) using an internal clock synchronized with an external clock as a delay monitoring clock source and a comparison standard clock source. The inventive register controlled DLL includes a first delay line; a second delay line; a delay model; a phase comparison means; a shift register control means; a master shift register; and a slave shift register.
A bidirectional shift register is disclosed which comprises a first and second flip-flop, a first multiplexer having an output coupled to an input of the first flip-flop, and a second multiplexer having an output coupled to an input of the second flip-flop wherein an output of the first flip-flop is coupled to an input of the second multiplexer, an output of the second flip-flop is coupled to an input of the first multiplexer.
The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices, a memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes an input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-skew to the data buffers and/or the memory devices.
