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Microelectronic packages with solder interconnections
   
Document Number
US Patent 6335222
Issued Date
January 1, 2002
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Abstract
A soldered assembly such as a packaged semiconductor chip includes elongated solder columns connected to the pads on the chip and a dielectric sheet having pads connected to the distal ends of the solder columns remote from the chip. Terminals on the sheet are connected to the pads of the sheet. The assembly can be handled and mounted using conventional surface-mount techniques, but provides thermal fatigue resistance. The solder columns may be inclined relative to the chip surface, and may contain long, columnar inclusions preferentially oriented along the lengthwise axes of the columns.
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Microelectronic packages with solder interconnections - US Patent 6335222 Drawing
Drawing from US Patent 6335222
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Number of Claims:
28
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Owner
Tessera, Inc. (San Jose, CA)
Published
January 1, 2002
Application Number
09/157,047
Filed
September 18, 1998
US Classification
438/108   257/E21.503 257/E21.511 438/612
Int'l Classification
H01L   21/56   (20060101)   H01L   21/60   (20060101)   H01L   21/02   (20060101)   H05K   3/34   (20060101)  
Examiner
Parent Case
CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims benefit of U.S. Provisional Patent Application No. 60/059,225, filed Sep. 18, 1997, the disclosure of which is hereby incorporated by reference herein.
USPTO Field of Search
438/615   438/128   438/108   438/612   438/613  
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Claims
Description
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