MOS Cascode amplifier circuits are subject to long-term or instantaneous changes (degradation) of performance characteristics by excess substrate currents. These currents can be generated in the grounded source transistor of the cascode connected output transistors during peak excursions of drain-source voltage across the grounded source transistor when the output voltage of the MOS Cascode amplifier circuit is at a maximum. An improved MOS Cascode amplifier circuit arrangement includes a voltage limiting bias circuit arrangement of additional transistors. The bias circuit arrangement acts as a series voltage-limiting device between the MOS Cascode amplifier circuit output node and the drain node of the upper-most cascode connected transistors when the MOS Cascode amplifier circuit output voltage is at its maximum value. An embodiment of the improved MOS Cascode amplifier circuit arrangement is arranged to limit the drain-source voltage excursion peak on the sensitive cascode transistor to a value below a pre-selected critical voltage, Vcrit. Vcrit is defined as the drain-source voltage value for the sensitive cascode transistor for which the instantaneous and/or cumulative substrate current caused by peak drain-source voltage excursions greater than Vcrit would instantaneously or cumulatively degrade the transistor's sensitive electrical parameters to an extent that would degrade (an) amplifier performance characteristic(s) to an appreciable degree. The additional transistors of one embodiment of the bias circuit arrangement are connected by internal adjacent source-drain nodes as a sequential chain with gates biased at respective fixed voltages. One external drain node of the chain connects to the output node of the MOS cascode amplifier and one external source node of the chain connects to drain of the uppermost cascode connected transistors. The number of additional transistors and the fixed bias gate voltages are selected to limit the peak drain-source voltage excursion on the sensitive transistor under selected operating conditions.
Example embodiments of the invention may provide systems and methods for a power amplifier. The systems and methods may include a first common-source device having a first source, a first gate, a first drain, and a first body, where the first source is connected to the first body, and wherein the first gate is connected to an input port. The systems and methods may further include a second common-gate device having a second source, a second gate, a second drain, and a second body, where the second source is connected to the first drain, where the second source is further connected to the second body, and where the second drain is connected to an output port.
A hot carrier lifetime of a MOS transistor is estimated, depending on model formulas: 1/.tau.=1/.tau..sub.0+1/.tau..sub.b; .tau..sub.b.varies.1.sub.sub.sup.-mbI.sub.d.sup.mb-2exp(a/|V.sub.bs|), where .tau. denotes a lifetime, I.sub.sub denotes a substrate current, I.sub.d denotes a drain current, V.sub.bs denotes a substrate voltage, .tau..sub.0 denotes a lifetime at the time the substrate voltage V.sub.bs=0, .tau..sub.b denotes a quantity representing deterioration of a lifetime at the time the substrate voltage |V.sub.bs|>0, and mb and `a` are model parameters. Furthermore, a parameter Age representing a cumulative stress quantity is calculated depending on model formulas: Age=Age.sub.0+Age.sub.b; Age.sub.b=.intg.1/H.sub.b[I.sub.sub.sup.mbI.sub.d.sup.2-m]exp(-a/|V.sub.b- s|)dt, where t denotes time, H.sub.b is a model parameter, Age.sub.0 denotes a parameter representing a cumulative stress quantity at the time the substrate voltage V.sub.bs=0, and Age.sub.bs denotes a quantity representing an increase of the cumulative stress quantity at the time the substrate voltage at |V.sub.bs|>0. Thereby, a lifetime in actual use is determined with accuracy even when a substrate voltage is applied, and circuit characteristic degradation is simulated with high accuracy.
A cascode-connected amplifier circuit including two transistors cascode-connected to each other, where a first transistor having a grounded emitter or a first field-effect transistor having a grounded source, and (a) a second transistor, having a grounded base, which is cascode-connected to the first transistor or to the first field-effect transistor, or (b) a second field-effect transistor, having a grounded gate, which is cascode-connected to the first transistor or to the first field-effect transistor. The cascode-connected amplifier circuit includes a switching element causing a collector of the first transistor or a drain of the first field-effect transistor to be grounded.
A system and method are described for separating the bulk connections for FETs on a semiconductor wafer from the supply rails, testing the wafer to determine if a shift in the threshold voltage, V.sub.T, of certain devices within the wafer, as defined by the bulk-wells, can remove an AC defect in the IC circuit, and tailoring the voltage or voltages applied to the bulk nodes, post-manufacture, such that the integrated circuit meets its performance targets or is sorted to a more valuable performance level. The method requires generating a gate level netlist of the IC's circuitry and performing timing calculations on these circuit netlists using static timing analyses, functional delay simulations, circuit activity analyses, and functional performance testing. The failures are then correlated to respective IC circuits, worst case slack circuits are investigated, and proposed changes to the threshold voltages are employed in the hardware.
A rail-to-rail class AB output stage includes a P-channel pull-up transistor (4) having a source coupled to a first supply rail voltage (V.sup.+), a gate coupled to a first input conductor (2) of the output stage, and a drain coupled to an output terminal (6) of the output stage. An N-channel pull-down transistor (5) includes a source coupled to a second supply rail voltage (GROUND), a gate coupled to a second input conductor (3) of the output stage, and a drain coupled to the output terminal (6). A P-channel first bias transistor (20) includes a source coupled to the first input conductor (2) and a drain coupled to the second input terminal (3). A first bias circuit coupled between the first and second supply rail voltages produces a first bias voltage (21) on a gate of the first bias transistor (20). A P-channel second bias transistor (10) includes a source coupled to be first input conductor (2). An N-channel third bias transistor (11) includes a source coupled to the second input terminal (3) and a drain connected to a drain of the second bias transistor (10) and to a non-inverting input of a servo amplifier (12) having an output coupled to a gate of the second bias transistor (10) and an inverting input coupled to a gate of the third bias transistor (11) or a suitable reference voltage. A second bias circuit coupled between the first and second supply rail voltages produces a second bias voltage (16) on the gate of the third bias transistor (11) and the inverting input of the servo amplifier.
