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Claims  |
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What is claimed is:
1. A method for estimating a code phase of a linear code defined by a polynomial, generating the linear code by sequential shifting a code generator of M stages, the method
comprising the steps,
constructing a reduced state space by mapping the M stages into M-tuple length possible branchwords and by mapping the M-tuple length possible branchwords into transitions of the reduced state space of possible states each of N length defining
N-tuple states conforming to the polynomial where N is less than M and where the possible branchwords define possible paths through the reduced state space extending from initial states through intermediate states to ending states,
transmitting the linear code as transmitted symbols,
receiving the transmitted symbols as received symbols received arbitrarily in time establishing the code phase relative in time,
grouping the received symbols into received branchwords of M length,
computing path metrics for the possible paths by searching from the initial states through the intermediate states to the ending states of the possible states within the reduced state space by metric comparison of the possible branchwords with
the received branchwords, and
estimating the code phase by selecting within the reduced state space one of the initial states having a preferred path of the possible paths to one of the ending states, which preferred path corresponds to a best metric of the computed path
metrics.
2. The method of claim 1 wherein,
the code generator is an M stage feedback shift register having an input equated by the polynomial to one or more taps of the M stages, and
the polynomial is an equation defining the linear code and equating the input to the taps of the M stages.
3. The method of claim 1 wherein,
the code generator is an M stage feedback shift register having an input to the M stages where the input is equated by the polynomial to N-1 taps of the M stages,
the polynomial is an equation defining the code sequence, and
the input and N-1 taps define N-tuple states of the reduced state space.
4. The method of claim 1 wherein,
the code generator is an M stage feedback shift register having an input to the M stages where the input is equated by the polynomial to N-1 taps of the M stages,
the polynomial is an equation defining the linear code,
the input and N-1 taps define the N-tuple states of the reduced state space,
the polynomial provides an equation relationship between the input and the N-1 taps, and
the equation relationship limits the number of the possible paths between states to constrain the searching to limit the number of the possible paths upon which the path metrics are computed.
5. The method of claim 1 wherein the linear code is a sequence of code chips, the method further comprising the steps of
modulating a data stream of data bits by combining the sequence of code chips with the data bits.
6. The method of claim 1 wherein the linear code is a sequence of code chips, the method further comprising the steps of
generating the code chips at a chipping rate,
generating a data stream of data bits at a data rate lower than the chipping rate at a multiple of the data rate,
modulating the data stream of data bits by modulo two summing of the code chips with data bits to spectrum spread the data stream of data bits each into a plurality of the transmitted symbols.
7. The method of claim 1 wherein the linear code is a series of code chips having a code length equal to (two to the power of M) minus 1, the method further comprising the steps of
modulating a data stream of data bits by combining the series of code chips with the data bits.
8. The method of claim 1 further comprising the steps of,
setting a metric threshold value,
determining when the computed path metrics are higher than the metric threshold value, and
terminating the searching along one of the possible paths when a respective one of the path metrics exceeds the metric threshold value to constrain the search to limit to metric.
9. The method of claim 1 further comprising the steps of,
setting a metric threshold value,
determining when the computed path metrics are higher or lower than the metric threshold value by a predetermined metric adaptive value,
resetting adaptively the metric threshold value higher or lower when the computed path metrics are respectively higher or lower than the metric threshold value by the predetermined metric adaptive value, and
terminating the searching along one of the possible paths when a respective one of the path metrics exceeds the metric threshold value to constrain the searching to limit metric computation.
10. The method of claim 1 wherein the computing step the possible states and possible paths are defined by a trellis transition diagram.
11. The method of claim 1 wherein the computing step, the possible states and possible paths are defined by a tree diagram.
12. A method for estimating a code phase of a direct sequence code defined by a polynomial, generating the direct sequence code by sequential shifting a code generator of M stages, the method comprising the steps,
constructing a reduced state space by mapping the M stages into M-tuple length possible branchwords and by mapping the M-tuple length possible branchwords into transitions of the reduced state space of possible states each of N length defining
N-tuple states conforming to the polynomial where N is less than M and where the possible branchwords define possible paths through the reduced state space extending from initial states through intermediate states to ending states,
generating the direct sequence code as a sequence of code chips at a chipping rate by the code generator comprising an M stage feedback shift register having an input to the M stages where the input is equated by the polynomial to N-1 taps of the
M stages, the polynomial is an equation defining the direct sequence code sequence, the input and N-1 taps define the N-tuple states of the reduced state space, the polynomial provides an equation relationship between the input and the N-1 taps,
generating a data stream of data bits at a data rate lower than the chipping rate at a multiple of the data rate,
modulating the data stream of data bits by modulo two summing of the code chips with data bits to spectrum spread the data stream of data bits each into a plurality of symbols,
transmitting the plurality of symbols as a sequence of transmitted symbols,
receiving the transmitted symbols as received symbols arbitrarily in time establishing the code phase relative in time,
grouping the received symbols into received branchwords of M length,
computing path metrics for the possible paths by searching from the initial states through the intermediate states to the ending states of the possible states within the reduced state space by metric comparison of the possible branchwords with
the received branchwords, the equation relationship limits the number of the possible paths between the N-tuple states to constrain the searching to limit the number of the possible paths upon which the path metrics are computed, and
estimating the code phase by selecting within the reduced state space one of the initial states having a preferred path of the possible paths to one of the ending states, which preferred path corresponds to a best metric of the computed path
metrics.
13. The method of claim 12 further comprising the steps of
setting a metric threshold value,
determining when the computed path metrics are higher than the metric threshold value, and
terminating the searching along one of the possible paths when a respective one of the path metrics exceeds the metric threshold value to constrain the searching to limit metric computation.
14. The method of claim 12 further comprising the steps of,
setting a metric threshold value,
determining when the computed path metrics are higher or lower than the metric threshold value by a predetermined metric adaptive value,
resetting adaptively the metric threshold value higher or lower when the computed path metrics are respectively higher or lower than the metric threshold value by the predetermined metric adaptive value, and
terminating searching along one of the possible paths when a respective one of the path metrics exceeds the metric threshold value to constrain the searching to limit metric computation.
15. The method of claim 12 wherein, the data stream is a static data stream so that the sequence of code chips are unmodulated by the data stream, the received symbols are an unmodulated pilot tone sequence of code chip symbols, and the code
phase is a pilot code phase and the code phase determination is a pilot code phase determination of the pilot code phase of the pilot tone sequence of code chip symbols, the method further comprising the steps of,
demodulating a second sequence of transmitted symbols having a second code phase displaced from the pilot code phase.
16. A method for estimating the code phase of a code defined by a polynomial derived from M stages of a code generator providing the code, the method comprising the steps,
constructing a reduced state space by mapping the M stages into M-tuple length possible branchwords and by mapping the M-tuple length possible branchwords into transitions of the reduced state space of possible states each of N length defining
N-tuple states conforming to the polynomial where N is less than M and where the possible branchwords define possible paths through the reduced state space extending from initial states through intermediate states to ending states,
generating the code as a sequence of code chips at a hopping rate by the code generator comprising an M stage feedback shift register having an input to the M stage where the input is equated by the polynomial to N-1 taps of the M stages, the
polynomial is an equation defining the code, the input and N-1 taps define N-tuple states of the reduced state space, the polynomial provides an equation relationship between the input and the N-1 taps,
frequency hopping a carrier signal, the hopping being between a plurality of frequencies respectively corresponding to the possible states,
modulating the carrier with a data stream of data bits as a modulated carrier signal,
transmitting the modulated carrier signal
receiving the modulated carrier signal,
generating a plurality of branchwords respectively corresponding to the plurality of frequencies, the modulated carrier signal arriving arbitrarily in time establishing the code phase relative in time,
computing path metrics for the possible paths by searching from the initial states through the intermediate states to the ending states of the possible states within the reduced-state space by metric comparison of the possible branchwords with
the received branchwords, the equation relationship limits the number of possible paths between states to constrain the sequential search by limiting the number of possible paths upon which the path metrics are computed, and
estimating the code phase by selecting within the reduced-state space one of the initial states having a preferred path of the possible paths to one of the ending states, which preferred path corresponds to a best metric of the computed path
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Claims |
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Description |
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FIELD OF THE INVENTION
The invention relates to the field of Communication systems and more particularly to Direct Sequence Spread Spectrum communication systems.
BACKGROUND OF THE INVENTION
Direct Sequence Spread Spectrum (DSSS) is a commonly used method for protecting communication and navigation signals against both jamming and unintentional interference, and for providing code division multiple access (CDMA), in which multiple
DSSS signals may share the same bandwidth. DSSS signals are widely used to provide protection against narrowband interference and reduce multipath signals within predetermined bandwidths. Spread spectrum systems provide signal security, frequency
management, and jamming and noise immunity.
A DSSS signal includes a pseudo-random sequence, that is, a direct sequence, spreading code modulated by a data stream. A CDMA channel bandwidth may be used for transmitting a plurality of superimposed DSSS signals each comprising a respective
unique data stream modulating a respective unique spreading code signal. The DSSS modulation requires the generation of a pseudo-random sequence of chips, that is, spreading code bits of zeros and ones, as the spreading code. The chips are communicated
as digital symbols. There is a predetermined number of chips per each data bit, with the data bits and code chips combined in synchronism. A remote transmitter code generator generates the spreading code at a chipping rate typically much higher than
the data bit rate of the data stream so that the direct sequence spreading code can be modulated by the lower bit rate of the digital data stream so as to spread the bandwidth of the data stream by the chipping rate over CDMA bandwidth. The modulation
of the spreading code by the data stream effectively spreads bandwidth of the data stream over the CDMA bandwidth. The symbol or chipping rate of the spreading code must be higher than the data rate of the underlying data stream, for example, ten
thousand times faster, for spectrum spreading with high processing gain equal in dB to ten times the log of the ratio of the bandwidth of the chipping rate divided to the bandwidth of data modulated by the chips. The digital chips of the spreading code
are added modulo two to the respective underlying data stream. The resulting sequence of chips has a symbol rate equal to the chipping rate of the spreading code. The spreading code is used to spread the data stream bandwidth. Several DSSS signals
have respective unique spreading codes that are typically transmitted by superposition within the CDMA bandwidth communicating the plurality of DSSS signals.
The spreading codes are chosen so that the cross correlation between different codes, of respective DSSS signals, is low. Low cross correlation between different spreading codes ensures that the correlation process upon reception will isolate
only the DSSS signal and the data bit stream of interest that corresponds to the selected spreading code while rejecting the other DSSS signals that share the CDMA bandwidth. Typically, the spreading codes are linear recursive sequences in which each
chip is the modulo two sum of a fixed set of preceding chips. Sequences of this type are usually generated as the output of a linear feed back shift register. The register is tapped at the locations corresponding to the chips that are to be summed and
the modulo two sum is fed back into the first stage of the shift register. To begin the process, a vector must be loaded into the shift register. The vector must be a non-zero vector to avoid a constant zero sequence. This vector is referred to as the
initial fill word or initial state. For DSSS applications, it is desirable that the sequences be pseudo-random and long. Only certain choices of taps in the shift register produce sequences of desirable cross correlation properties and maximum length.
The shift register taps correspond to the non-zero coefficients of a generating polynomial function for the DSSS code sequence. An identical polynomial function may be implemented using the same shift register feedback structure in the receiver to
locally generate the same code sequence for despreading with the same initial fill word.
Upon reception, the spreading code is used to despread the CDMA channel to isolate and acquire the particular DSSS signal of interest and to then recover the underlying digital data of the digital data stream. The DSSS signal has a bandwidth
larger than the digital bit stream by virtue of modulating the data stream at the higher chipping rate, that is, at the frequency of the spreading code. The spreading code is generated at a higher frequency and is modulated by the digital data bit
stream having a lower frequency, and hence the digital data bit stream is spread from a narrow data rate bandwidth across the larger bandwidth defined by the higher chipping rate, that is, the symbol rate.
The receiver of a DSSS signal requires the generation of the same spreading code for correlation detection of the respective particular modulated data stream of interest. The receiver typically locally generates the same spreading code. The
data stream is recovered from the DSSS signal by correlating the locally generated replica of the spreading code with the received DSSS signal. The correlation process removes the spreading code by despreading the DSSS signal back into the underlying
data stream and increases the strength of the received signal by a factor equal to the processing gain equal to the bandwidth of the DSSS signal divided by the bandwidth of the underlying data stream. The DSSS bandwidth is thereby effectively compressed
back into the bandwidth of the underlying data stream.
In practice, a DSSS signal or a plurality of DSSS signals may further modulate a high frequency carrier signal suitable for radio frequency transmission. There are many types of carrier modulation methods used, such as Binary Phase Shifted
Keyed, (BPSK), Quadrature Phase Shift Keyed (QPSK) and Gaussian Minimum Shift Keyed (GMSK) carrier modulation methods. Further still, the data bits of the data stream may be formatted before producing a modulated data stream. There are many types of
data stream data modulation methods, such as, non-return to zero (NRZ), and Manchester (Bi-Phase-L) data stream modulation methods. Upon reception, the carrier signal is typically demodulated using tracking, Costas loop or squaring loop carrier
demodulators, to produce the digital stream. The data of the data stream is then demodulated using data bit synchronizers to detect data bits at the data rate to recover the data bits from the data stream. Carrier modulation and data stream modulation
during transmission, and, carrier demodulation and data stream demodulation during reception typically occur in addition to the spreading and despreading of the DSSS signal over the CDMA bandwidth. Carrier and data stream modulation and demodulation are
well known to those skilled in the art of spread spectrum systems.
A DSSS signal is received by a DSSS receiver that recovers the data of the spread spectrum data stream. The DSSS receiver must not only generate a replica of the chip sequence of the spreading code for DSSS despreading, but must also time shift
the locally generated replica to be aligned in time with the remotely generated spreading code in the received DSSS signal to within a fraction of a chip interval so that the correlation produces a despread signal. The time shift between the locally
generated spreading code and the remotely received spreading code in the received DSSS signal is related to a specific number of chips in the spreading code at the chipping rate. Hence, the time shift offset between the received spreading code and the
replica despreading code establishes a code phase. Determining this time shift code phase for correlation alignment is necessary to recover the data stream and is known as code phase acquisition, or more simply code acquisition. When the locally
generated despreading code is in time alignment, then the despreading correlation will isolate only that DSSS signal of interest having the same spreading code and code phase. Demodulation of the DSSS signal upon reception is accomplished by correlation
of the received CDMA signals with a replica of the spreading code used in the transmitter to despread the CDMA signal and hence despread only one of the superimposed DSSS signals, that is, the desired DSSS signal of interest containing the particular
spreading code signal to isolate the desired digital data stream. The transmitted spreading code and the identical despreading code enable the spreading, superpositioning, and despreading isolation of many DSSS signals within a CDMA channel bandwidth.
It is therefore necessary for the receiver to acquire, that is, determine the code phase between an arrived transmitted spreading code and the receiver locally generated despreading code, in order to isolate by correlation a particular DSSS signal upon
reception.
The DSSS receiver is required to determine code phase for DSSS signal acquisition. After the spreading code is remotely generated within the transmitter and the data stream to be communicated is remotely modulated by the spreading sequence by
modulo two summing the spreading code with the data stream, the DSSS signal is then typically transmitted asynchronously to the DSSS receiver. The DSSS receiver locally generates the spreading code as an identical despreading code to demodulate by
correlation the DSSS signal. However, and importantly, the arrival time of the remotely generated spreading code will not be in code phase synchronization with locally generated despreading code, and as such will prevent correlation despreading of the
DSSS signal. Code phase determination, is in effect, a determination of the amount of time displacement between the arrival of the remotely generated spreading code and the locally generated despreading code, both typically initiating the code sequence
at differing arbitrary points in time creating an inherent time differential. By delaying the locally generated spreading code by that time differential, that is, by the code phase amount of time, the received spreading code and the despreading code can
be aligned in time for correlation demodulation of the DSSS signal to recover the desired data stream.
Hence, the code phase time shift inherently results from generating the spreading code initiated at one point in time in the transmitter in relation to a receiver using the same despreading code initiated at another point in time. The
unsynchronized initiations of the spreading and despreading code, in addition to variable transmission delays, create the time differential, that is, the code phase. The despreading of the DSSS signal will only occur when the reception of the remotely
transmitted spreading code is aligned in time in the receiver to the locally generated receiver despreading code, after the code phase has been determined for DSSS acquisition. After code phase acquisition, the output of the correlation function upon
reception, ideally, is a constant that, after integration of the correlated signal, can establish a threshold level to determine, that is, detect the presence of the desired DSSS signal, upon which, data stream demodulation is used to recover the actual
data bits of the data stream. After code acquisition, code tracking continuously monitors the integration output to keep the system in code phase lock. It is desirable that the time required for code acquisition be small as possible for rapid
acquisition of the data bits of the data stream for improved performance.
The code phase is effectively set by the initiation of the contents of the receiver shift register feedback structure at an arbitrary point in time relative to the reception of the transmitted spreading code. The initial state, that is, the
contents of the M-stage shift register, is described by a binary fill word, which must be chosen to be a non-zero binary vector of length M chips. An exemplar M stage register is used and may be of any suitable arbitrary length M. The feedback taps are
typically selected to ensure that the output direct sequence code, that is, the spreading code, is a maximum-length linear sequence, that is, an m-sequence, having a length m equal to 2.sup.M -1, although other suitable lengths and spreading codes may be
used as long as the sequence has desirable auto-correlation and cross-correlation properties to isolate the DSSS signal. The conventional DSSS method is not restricted to the use of m-sequence spreading codes.
Hence, one fundamental problem with DSSS systems is the time required for code phase determination, that is, code acquisition, based upon the time uncertainly associated with the time of arrival of the transmitted spreading code. The time clock
of the transmitters and receivers are typically not in time synchronism, and the transmission delays between the transmitter and receiver may vary over time. Hence, DSSS systems have an inherent time delay associated with signal transmissions, and as
such, lack inherent time synchronization between the reception of the transmitted spreading code and the receiver locally generated despreading code. The lack of time synchronization creates a code phase between the received spreading code and the
locally generated despreading code. In order to acquire the data stream, the code phase is firstly determined to acquire time synchronization, that is, chip synchronization, between the transmitted spreading code of the transmitted signal and receiver
despreading code of the locally generated despreading code in the receiver. Upon code phase determination, the transmitted code of the received spread spectrum signal and the locally generated spreading code are matched in time to despread the DSSS
signal by correlation to isolate the data stream of interest to then recover the data bits from the DSSS signal. Conventional DSSS systems have relied upon various methods to solve this fundamental code acquisition problem, that is, the problem of
rapidly determining code phase. The code acquisition ensures that the receiver shift register generates the spreading code that exactly matches the spreading code generated in the transmitter, by determining the code phase to compensate for channel
delays and a lack of synchronization between the transmitter and receiver. Rapid acquisition of the digital signal is desirable and facilitates improved use of the available bandwidth. Thus, rapid acquisition methods are desirable in DSSS systems.
Prior solutions to the code acquisition problem include the load and go method, the sliding correlator method, the time reference method, the collateral short code method, and related variants.
The load and go method for rapid code acquisition has been used to estimate a code phase by estimating a fill word of the plurality of fill words. A plurality of differing fill words can be used to generate the spreading code sequence at
respective offset times. The method is an estimate in the presence of corrupted received code chips communicated across a noisy channel providing a low signal to noise ratio. A variety of techniques have been used to derive the fill word estimates.
The load and go method can achieve rapid code acquisition but only if the signal to noise ratio is high. The starting point in time or code phase is not known, and hypothesis testing over many sequence code phases may be needed to determine code phase.
A local replica of the spreading code is generated during reception using a shift register with the same feedback taps and with one of the plurality of fill words as initial register contents that may be the same initial contents that were used in the
transmitter. The receiver assumes that the last M chip set is an error free fill word and loads these M chips into the receiver feedback shift register. The receiver then compares the locally generated chip sequence to subsequently received chips to
check the correctness of the assumed fill word. This search method determines the code phase between the transmitted spreading code and the identical locally generated despreading code during the code acquisition process. If the received signal has
many chip errors, then the "load and go" process will have to be repeated many times and may not work at all in high noise situations.
The sliding correlator method introduces successive time differentials during the generation of the locally generated despreading code. The local despreading code chips are successively offset by sequential chip shifts of the locally generated
despreading code relative to the received spreading code. The locally generated despreading code is successively shifted by typically one half chip time creating successively larger time offsets of the code phase until time synchronization occurs
between the received spreading code and the locally generated despreading code, where the number of shifted chips determines the code phase, that is, the accumulative time shift of the received chips. Once the code phase is determined by correlation
integration detection, the received signal is despread to demodulate DSSS signal to then produce the digital data stream during signal tracking. One disadvantage of this method is the long acquisition time associated with the successive sequential
sliding chip shifts of the sliding correlator. The sliding correlator method is slow when searching in a large epoch time uncertainty situation especially over long code sequences that can last weeks in duration to complete one full sequence. The
sliding correlator method can be very slow and typically and disadvantageously also adds significant complexity to the receiver while introducing long delays in acquiring the code phase.
The time reference method for solving the rapid code acquisition problem uses a precise time reference at the receiver to estimate code epoch time. This method may be adapted to use an auxiliary transmitter and receiver to transfer a precise
time reference from the transmitter to the receiver. The time reference method disadvantageously requires the use of precise internal and external time references and adds further complexity and limitations to the code acquisition process.
The collateral short code method is yet another method of rapid acquisition which firstly and rapidly determines code phase of a short spreading code that is time referenced to the subject long spreading code for determining the code phase of the
long code. The short spreading code is used in conjunction with a time synchronized long spreading code. The collateral short code method disadvantageously acquires a DSSS signal using the short code that is in precise time synchronization to a longer
code, such that, the phase code determination of a short code aids in directly determining the code phase of long spreading code modulated by the desired data stream. This method disadvantageously requires the use of dual spreading code systems having
predetermined code phase relations between the short and long spreading codes. Such a dual code system can significantly increase both receiver complexity and cost.
Another fundamental problem associated with all communication systems, including DSSS systems, is the noisy communication channels through which the signals are transmitted, communicated, and received. Many communication channels are modeled as
additive white Gaussian noise channels. The communication channel may also be subjected to intentional and unintentional interference and multipath distortions. These noisy channels create errors typically modeled as random data bit and code chip
errors in both the data stream and chip code sequences, respectively. Many of the code symbols of the spreading code sequence are received in error due to noise. This causes errors in many of the data bits of the digital data stream. Real world code
acquisition processes disadvantageously suffer from data and chip error uncertainties, complicating the rapid acquisition process.
Digital communication systems have used convolutional error correction techniques to correct data transmission errors. These convolution techniques typically include a transmitter binary convolution process transmitting redundant code bits
convolved with the data bits. An inverse convolutional decoder is used to retrieve the data from the convolved encoded signal through a convolutional decoder using trellis, tree, or sequential search error correcting techniques. Typically, the output
of the inverse convolution decoder is subject to transmission errors in the convolved digital code and data bits. The initial state of the decoder, as viewed from any arbitrary point along a data stream, is generally not known. By accumulating relative
probabilities of state transitions, a probable state to state transition path can be calculated to estimate the current state, and to then compute data that should have been received to enable the correction of data errors. While convolutional coding
methods have been used for data error correction, these convolutional error correcting techniques have disadvantageously not been coupled together with DSSS systems to estimate initial states for code phase determination for rapid acquisitions of a
particular DSSS signal. These and other disadvantages are solved or reduced using the invention.
SUMMARY OF THE INVENTION
An object of the invention is to provide a method for rapid acquisition of Direct Sequence Spread Spectrum (DSSS) signals comprising spreading codes of chips.
An object of the invention is to provide a method for rapid acquisition of DSSS signals comprising spreading codes of chips modulating a data stream providing a sequence of symbols.
Another object of the invention is to use a reduced state structure for estimating current states of received chip values for resolving chip uncertainties.
Another object of the invention is to simplify DSSS receivers by providing a means of demodulating data bits without generating a local time synchronized version of the spreading code.
Another object of the invention is to apply convolutional decoding principles to estimate the code phase of a DSSS signal.
Another object of the invention is to apply convolutional decoding to estimate epoch time of a sequence of code chips.
Another object of the invention is to apply convolutional decoding to estimate code phase of a sequence of symbols.
Another object of the invention is to apply convolutional decoding to estimate epoch time of a sequence of code chips.
The present invention is applied to any linear code sequence in which each chip is the modulo two sum of a fixed number of preceding chip. The invention is preferably a rapid acquisition method of rapid acquisition of DSSS signals comprising
spreading code chips. This rapid acquisition method is herein referred to as a convolutional despreading method. The use of the method enables rapid demodulation of a data stream of data bits. The transmitter and receiver structure can be adapted to
function in both a noisy environment and in the presence of other spreading codes as in a CDMA environment. The transmitter includes a spreading code generator having a feedback shift register having a predetermined number of M stages and taps defining
a polynomial equation for generating a particular direct sequence code of code chips which modulate the data stream. The received DSSS signal is firstly received, digitized and fed into a delay register having a predetermined number of stages and tapped
outputs. The delay register is preferably an M+1 stage tapped serial bit shift register. The delay register provides outputs as branchwords for implementation of a search algorithm to perfect the convolutional despreading method. The delay register is
further defined as a state machine having a reduced state map of less than 2.sup.M states. The delay shift register, viewed as a finite state machine, then is modeled to transit only among the reduced number of states. The polynomial equation provides
a computational relationship between the states. A metric state processor receives the tapped outputs from the delay shift register, and calculates a state transition metric to provide an estimate of the initial state of the delay shift register, to
estimate the code phase and initial states of the reduced state structure. The reduced number of states leads to rapid metric calculation and initial state estimates. The estimate of the initial state defines the actual code phase of the chip sequence
of symbols that have been received. The state processor can further provide demodulated data recovered from the received symbol sequence, and can further provide a code epoch time estimate.
In the preferred use of the method, a transmitter generates a DSSS baseband signal comprising a data stream of digital data bits modulated by a spreading code of a sequence of code chips initiated at an arbitrary point in time. Typically, such a
transmitter will include a tapped feedback shift register generating the spreading code which modulo two sums with the data bits to spread the data stream over a predetermined bandwidth. An improved DSSS receiver may include channel filtering, but
preferably includes an analog to digital means for converting the transmitted DSSS baseband signal into digital type signals that are then fed into the delay register having state outputs fed into the metric state processor that then provides the initial
estimates of code phase. The code phase can be used to provide a receiver conventional M stage feedback shift register with initial fill words for regeneration of the despreading code for conventional correlation to acquire the data stream for data
recovery. The improved receiver can also operate continuously without the use of a conventional correlation receiver.
The convolutional despreading method reformulates the code acquisition problem into a convolutional decoding problem where the receiver includes a finite state machine having a reduced state set, and a metric state processor operating on the
reduced set of states and transitions between those states to provide the estimate of initial code phase. The state processor can implement various convolution searching techniques based upon best path metrics computations, such as, the preferred
Virterbi trellis or Fano tree search algorithms that are sequential search algorithms searching for the most likely path through a corresponding reduced state transition structure.
For a DSSS system, rapid estimation of the initial state, and therefore the code phase, reduces the time required to acquire the DSSS signal and achieve successful demodulation of the underlying data while leading to reduced complexity of DSSS
receivers. For a hopping system, an analog to digital filter provides successive branchwords that correspond to the respective carrier frequencies, the rapid estimation method rapidly determines the hopping code phase. These and other advantages will
become more apparent from the following detailed description of the preferred embodiment.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of a sample channel baseband signal of a sequence of code chips modulating data bits into symbols of a five stage Direct Sequence spread spectrum (DSSS) system.
FIG. 2 is a diagram of a five-stage rapid acquisition DSSS system.
FIG. 3 is a transmitted branchword diagram for the five-stage DSSS system.
FIG. 4 is a state {0,0,0} tree diagram for the five-stage DSSS system for use with a modified Fano Tree convolutional search.
FIG. 5A is a reduced state diagram for when a data bit equals zero for the five-stage DSSS system.
FIG. 5B is a reduced state diagram for when a data bit equals one for the five-stage DSSS system.
FIG. 6 is a diagram of a sample channel baseband signal of a sequence of code chips modulating data bits into symbols of a four-stage DSSS system.
FIG. 7 is a diagram of a four-stage rapid acquisition DSSS system.
FIG. 8A is a reduced state diagram for when a data bit equals zero for the four-stage DSSS system.
FIG. 8B is a reduced state diagram for when a data bit equals one for the four-stage DSSS system.
FIG. 9A is a reduced trellis diagram for when a data bit equals zero for the four-stage DSSS system.
FIG. 9B is a reduced trellis diagram for when a data bit equals one for the four-stage DSSS system.
FIG. 10A is a transmitted branchword diagram for the four-stage DSSS exemplar sys | | |
