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Full wave rectifier circuit using normally off JFETs
   
Document Number
US Patent 6349047
Issued Date
February 19, 2002
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Inventors
Yu; Ho-Yuan (Saratoga, CA)
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Abstract
A four terminal full wave rectifier circuit that can be used as a pin for pin replacement for the full wave diode rectifier circuit commonly used in DC power supply circuits. Two full wave rectifier circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. Both circuits utilize two n-channel, enhancement mode Junction Field Effect Transistors (JFET) and two p-channel, enhancement mode Junction Field Effect Transistors to replace the rectifier diodes used in a conventional full wave rectifier circuit. The forward voltage drop across each JFET is considerably smaller than the forward voltage drop of a conventional rectifier. In a first configuration, the JFETs are all symmetrical about the source and drain leads. Starter devices are connected between source and drain leads and current limiting devices are in series with the gate leads. The gate leads of the JFETs are connected to the input terminals of the circuit such that a full wave rectified version of the input signal is produced at the output of the circuit. In a second configuration, two asymmetrical n-channel and two asymmetrical p-channel JFETs are used to replace the four rectifier diodes found in a conventional full wave rectifier circuit. The gate of each JFET is connected to its source lead and a full wave rectified version of the input signal is then produced at the output of this circuit.
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Full wave rectifier circuit using normally off JFETs - US Patent 6349047 Drawing
Drawing from US Patent 6349047
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Number of Claims:
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Owner
Lovoltech, Inc. (Santa Clara, CA)
Published
February 19, 2002
Application Number
09/741,488
Filed
December 18, 2000
US Classification
363/127  
Int'l Classification
H02M   7/219   (20060101)  
Attorney/Law Firm
Parent Case
RELATED APPLICATIONS The following copending U.S. patent application Ser. No. 09/430,500, "NOVEL JFET STRUCTURE AND MANUFACTURE METHOD FOR LOW ON RESISTANCE AND LOW VOLTAGE APPLICATIONS", Ho-Yuan Yu, filed Oct. 29, 1999, is incorporated herein by reference for all purposes. The following copending U.S. provisional patent application Ser. No. 60/167,959, "STARTER DEVICE FOR NORMALLY "OFF" JFETS", Ho-Yuan Yu, filed Nov. 29, 1999, and copending U.S. patent application, entitled "STARTER DEVICE FOR NORMALLY OFF JFETS," filed Nov. 7, 2000, Ser. No. 09/708,336, by Ho-Yuan Yu, are incorporated herein by reference for all purposes.
USPTO Field of Search
363/127  
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