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| United States Patent | 6349396 |
| Link to this page | http://www.wikipatents.com/6349396.html |
| Inventor(s) | Akram; Salman (Boise, ID) |
| Abstract | A burn-in testing system for evaluating a circuit under test, the system
including a burn-in board having a plurality of receptacles, at least one
of which being sized to receive the circuit under test, test interface
circuitry supported by the board and coupled to the receptacles, the test
interface circuitry including a transmitter and receiver; power conductors
supported by the board, coupled to the receptacles and configured to be
connected to a power supply to power the circuit under test during burn-in
testing, control and data signal conductors, a burn-in oven having a
compartment selectively receiving the burn-in board and being configured
to apply heat within the compartment, and an interrogator unit supported
by the burn-in oven, the interrogator unit being configured to send
commands to the test interface circuitry to exercise the circuit under
test optically or via radio communication and to receive responses to the
commands optically or via radio communication. A method for testing an
integrated circuit having operational circuitry formed thereon, optically
and via radio frequency. |
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Title Information  |
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| Publication Date |
February 19, 2002 |
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| Filing Date |
December 21, 2000 |
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| Parent Case |
CROSS REFERENCE TO RELATED APPLICATION
This is a Continuation of U.S. patent application Ser. No. 09/515,975,
filed Feb. 29, 2000, now U.S. Pat. No. 6,189,120, entitled "A Testing
System for Evaluating Integrated Circuits, A Burn-In Testing System, and a
Method for Testing an Integrated Circuit", listing Salman Akram as
inventor, which is a Continuation of U.S. patent application Ser. No.
09/009,973, filed Jan. 21, 1998, now U.S. Pat. No. 6,119,255. |
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Title Information  |
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References  |
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| *references marked with an asterisk below are user-added references |
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U.S. References |
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| | Reference | Relevancy | Comments | Reference | Relevancy | Comments | 3689885 Suzuki 713/340 May,2006 |      Your vote accepted [0 after 0 votes] | | 6189120 Akram 714/724 Feb,2001 |      Your vote accepted [0 after 0 votes] | | 6119255 Akram 714/724 Sep,2000 |      Your vote accepted [0 after 0 votes] | | 6058497 Tuttle
May,2000 |      Your vote accepted [0 after 0 votes] | | 5953688 Su 702/185 Sep,1999 |      Your vote accepted [0 after 0 votes] | | 5949246 Frankeny 324/765 Sep,1999 |      Your vote accepted [0 after 0 votes] | | 5945834 Nakata 324/754 Aug,1999 |      Your vote accepted [0 after 0 votes] | | 5801432 Rostoker 257/666 Sep,1998 |      Your vote accepted [0 after 0 votes] | | 5764655 Kirihata 714/733 Jun,1998 |      Your vote accepted [0 after 0 votes] | | 5672981 Fehrman 324/760 Sep,1997 |      Your vote accepted [0 after 0 votes] | | 5448110 Tuttle 257/723 Sep,1995 |      Your vote accepted [0 after 0 votes] | | 5343478 James 714/726 Aug,1994 |      Your vote accepted [0 after 0 votes] | | 5317255 Suyama 324/754 May,1994 |      Your vote accepted [0 after 0 votes] | | 5303199 Ishihara 365/225.7 Apr,1994 |      Your vote accepted [0 after 0 votes] | | 5274221 Matsubara 235/492 Dec,1993 |      Your vote accepted [0 after 0 votes] | | 5252914 Bobbitt 324/158.1 Oct,1993 |      Your vote accepted [0 after 0 votes] | | 5226167 Yamaguchi 332/107 Jul,1993 |      Your vote accepted [0 after 0 votes] | | 5220158 Takahira 235/492 Jun,1993 |      Your vote accepted [0 after 0 votes] | | 5219765 Yoshida 438/10 Jun,1993 |      Your vote accepted [0 after 0 votes] | | 5212373 Fujioka 235/492 May,1993 |      Your vote accepted [0 after 0 votes] | | 5202838 Inoue 702/57 Apr,1993 |      Your vote accepted [0 after 0 votes] | | 5198647 Mizuta 235/449 Mar,1993 |      Your vote accepted [0 after 0 votes] | | 5182442 Takahira 235/492 Jan,1993 |      Your vote accepted [0 after 0 votes] | | 5164665 Yamashita 714/744 Nov,1992 |      Your vote accepted [0 after 0 votes] | | 5148103 Pasiecznik, Jr. 324/758 Sep,1992 |      Your vote accepted [0 after 0 votes] | | 5113184 Katayama 340/10.51 May,1992 |      Your vote accepted [0 after 0 votes] | | 5068521 Yamaguchi
Nov,1991 |      Your vote accepted [0 after 0 votes] | | 4962485 Kato 365/229 Oct,1990 |      Your vote accepted [0 after 0 votes] | | 4930129 Takahira 714/766 May,1990 |      Your vote accepted [0 after 0 votes] | | 4833402 Boegh-Petersen 324/754 May,1989 |      Your vote accepted [0 after 0 votes] | | |
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References  |
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Claims  |
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What is claimed is:
1. A burn-in testing system for evaluating a circuit under test, the system
comprising:
a burn-in board having a plurality of receptacles, at least one of which is
configured to receive the circuit under test and to supply power thereto;
test inferface circuitry coupled to the receptacles, the test interface
circuitry including a transmitter and a receiver; and
an interrogator unit having a radio communication range extending to the
test interface circuitry, the interrogator unit being configured to send
commands via radio communication through the receiver to the test
interface circuitry to exercise the circuit under test and to receive
responses to the commands from the transmitter via radio communication.
2. A burn-in testing system in accordance with claim 1, wherein the test
interface circuitry is mounted to the burn-in board.
3. A burn-in testing system in accordance with claim 1, further comprising
power conductors supported by the burn-in board, coupled to the
receptacles and configured to be coupled to a power supply to power the
circuit under test during burn-in testing, wherein the power conductors
comprise conductive traces formed on the burn-in board.
4. A burn-in testing system in accordance with claim 1, further comprising
data lines supported by the burn-in board, coupled between the receptacles
and the test interface circuitry and configured to exchange information
between the test interface circuitry and the circuit under test.
5. A burn-in testing system in accordance with claim 1, further comprising
conductive traces formed on the burn-in board and configured to couple the
receptacles to the test interface circuitry.
6. A burn-in testing system in accordance with claim 1, wherein the circuit
under test includes operational circuitry, and wherein the test interface
circuitry cycles the operational circuitry according to the commands from
the interrogator unit.
7. A burn-in testing system in accordance with claim 6, wherein the
interrogator unit is configured to provide an identification code as part
of the interrogating information, wherein the test interface circuitry
includes ID labels assigned to respective receptacles, and wherein the
test inferface circuitry is configured to compare the identification code
provided by the interrogator unit with the ID label of a receptacle of the
plurality of receptacles corresponding to the circuit under test, the test
interface circuitry being configured to test cycle the operational
circuitry when the identification code matches the ID label.
8. A burn-in testing system in accordance with claim 1, wherein the test
interface circuitry is separately coupled to respective ones of the
plurality of receptacles such that the interrogator, in communication with
the test interface circuitry, can select the circuit under test for test
cycling.
9. A burn-in testing system in accordance with claim 1, wherein ones of the
plurality of receptacles respectively comprise sockets configured to
receive an integrated circuit comprising the circuit under test.
10. A burn-in testing system in accordance with claim 1, wherein at least
one of the plurality of receptacles is configured to receive an integrated
circuit defining the circuit under test.
11. A testing system for evaluating integrated circuits, the testing system
comprising:
an interrogator unit having a transmitter having a radio communication
range and configured to transmit interrogating information via radio
communication;
receiver configured for communications with the transmitter; and
a burn-in board remote from the interrogator unit, but within the radio
communication range, the burn-in board including a plurality of
receptacles configured to receive respective individual integrated
circuits and to supply power thereto, the burn-in board having burn-in
test conductors coupling the receiver to respective ones of the plurality
of receptacles, the plurality of receptacles including sockets configured
to electrically couple the respective integrated circuits to the burn-in
test conductors.
12. A testing system in accordance with claim 11, further comprising test
interface circuitry supported by the burn-in board, the test interface
circuitry including the receiver.
13. A testing system in accordance with claim 12, wherein the test
interface circuitry is formed on the burn-in board.
14. A testing system in accordance with claim 12, wherein the test
interface circuitry is configured to be separately coupled to the
respective ones of the plurality of receptacles for individualized testing
of integrated circuits.
15. A testing system in accordance with claim 11, wherein the testing
system is configured to perform dynamic testing.
16. A testing system in accordance with claim 11, wherein the testing
system is configured to perform dynamic testing and wherein the integrated
circuits are cycled on and off during a period of time greater than twelve
hours and less than thirty-six hours.
17. A testing device in accordance with claim 11, further comprising a test
chamber including a burn-in over, wherein the testing system is configured
to perform dynamic testing including cycling the integrated circuits on
and off during a period of time greater than twelve hours and less than
thirty-six hours while the oven heats the chamber to a temperature greater
than 100 degrees Celsius.
18. A testing system in accordance with claim 11, further comprising a test
chamber including a burn-in oven, wherein the testing system is configured
to perform dynamic testing including cycling the integrated circuits on
and off during a period of time of at least twelve hours while the oven
heats the chamber to a temperature greater than 100 degrees Celsius.
19. A testing system in accordance with claim 11, wherein the testing
system is configured to perform static testing.
20. A testing system in accordance with claim 11, further comprising power
conductors configured to couple respective ones of the plurality of
receptacles to a power source to supply power to the integrated circuits
during burn-in testing wherein the power conductors extend at least
partially along the burn-in board.
21. A testing system in accordance with claim 11, further comprising:
power conductors formed on the burn-in board and configured to couple
respective ones of the plurality of receptacles to a power source to
supply power to the integrated circuits during burn-in testing;
a burn-in oven configured to heat the test chamber during burn-in testing;
and
a power source accessible from the test chamber, wherein the power
conductors are configured to be removably coupled to the power source.
22. A testing system in accordance with claim 11, further comprising:
power conductors formed on the burn-in board and configured to supply power
to the integrated circuits during burn-in testing; and
a power source to which the power conductors are selectively coupled, the
power source being configured to supply to the integrated circuits a
voltage higher than a normal operating voltage of the respective
integrated circuits.
23. A burn-in testing system for evaluating a circuit under test, the
system comprising:
a burn-in board having a plurality of receptacles configured to
respectively receive the circuit under test;
test interface circuitry coupled to the receptacles, the test interface
circuitry including a first optical coupler; and
an interrogator unit including a second optical coupler and being
configured to optically send commands to the test interface circuitry, via
the second optical coupler, to test the circuit under test and to
optically receive responses to the commands, via the second optical
coupler.
24. A burn-in testing system in accordance with claim 23, wherein at least
one of the plurality of receptacles is configured to receive an integrated
circuit.
25. A burn-in testing system in accordance with claim 23, further
comprising a fiber optic cable configured to couple the interrogator unit
to the test interface circuitry.
26. A testing system for evaluating integrated circuits, the testing system
comprising:
an interrogator unit having an optical transmitter having an optical
communication range, the interrogator unit being configured to optically
transmit interrogating information;
an optical receiver configured to communicate with the optical transmitter;
and
a burn-in board included within the optical communication range, the
burn-in board including a plurality of receptacles configured to receive
respective individual integrated circuits and to supply power thereto, the
burn-in board supporting the optical receiver, the burn-in board having
burn-in test conductors configured to couple the optical receiver to
respective receptacles, the receptacles including sockets configured to
electrically couple the respective integrated circuits to the burn-in test
conductors.
27. A testing system in accordance with claim 26, further comprising test
interface circuitry supported by the burn-in board, the test interface
circuitry including the optical receiver.
28. A method for testing an integrated circuit including operational
circuitry, the method comprising:
providing test interface circuitry and a plurality of receptacles
configured to electrically interface the test interface circuitry with the
operational circuitry in the integrated circuits and to supply power
thereto;
providing an interrogator unit;
placing the integrated circuit in one of the plurality of receptacles;
heating the integrated circuit;
transmitting interrogating information from the interrogator unit to the
test interface circuitry via radio communication;
testing the operational circuitry according to the interrogating
information;
coupling test data from the operational circuitry to the interrogator unit;
and
determining whether the integrated circuit has a defect.
29. A method in accordance with claim 28, further comprising:
marking respective ones of the plurality of receptacles with individual ID
labels;
transmitting an identification code from the interrogator unit;
comparing the identification code with the ID label; and
test cycling the operational circuitry of an integrated circuit in a given
receptacle only when the identification code matches the individual ID
label of the given receptacle.
30. A method for testing an integrated circuit including operational
circuitry, the method comprising:
providing test interface circuitry and a plurality of receptacles
configured to receive integrated circuits and to electrically interface
the operational circuitry in the integrated circuits with the test
interface circuitry and to supply power thereto;
providing an interrogator unit;
placing the integrated circuit in one of the receptacles;
optically transmitting interrogating information from an optical
transmitter having an optical communication range and contained in the
interrogator unit to the test interface circuitry;
testing the operational circuitry according to the interrogating
information;
optically transmitting test data output by the operational circuitry back
to the interrogator unit; and
determining from the test data whether the integrated circuit has a defect.
31. A method in accordance with claim 30, further comprising:
marking respective ones of the plurality of receptacles with individual ID
labels;
transmitting an identification code from the interrogator unit;
comparing the identification code with the individual ID labels; and
test cycling the operational circuitry of an integrated circuit in a given
receptacle only when the identification code matches the individual ID
label of the given receptacle.
32. A method in accordance with claim 30, further comprising heating the
integrated circuit during testing.
33. A method for testing an integrated circuit including operational
circuitry, the method comprising:
providing test interface circuitry and a plurality of receptacles
configured to receive integrated circuits and to electrically interface
the operational circuitry in the integrated circuits with the test
interface circuitry and to supply power thereto;
providing an interrogator unit;
placing the integrated circuit in one of the receptacles;
transmitting interrogating information from the interrogator unit to the
test interface circuitry via radio communication; and
testing the operational circuitry according to the interrogating
information.
34. A method for testing an integrated circuit including operational
circuitry, the method comprising:
providing test interface circuitry and a plurality of receptacles
configured to receive integrated circuits, to electrically interface the
operational circuitry in the integrated circuits with the test interface
circuitry and to supply power thereto;
providing an interrogator unit;
placing the integrated circuit in one of the receptacles;
optically transmitting interrogating information from an optical
transmitter having an optical communication range in the interrogator unit
to the test interface circuitry; and
testing the operational circuitry according to the interrogating
information.
35. A method for testing an integrated circuit including operational
circuitry, comprising:
providing an interrogator unit;
coupling the integrated circuit to test interface circuitry via a
receptacle, the receptacle supplying power to the integrated circuit;
transmitting interrogating information from the interrogator unit to the
test interface circuitry via radio communication; and
testing the operational circuitry according to the interrogating
information.
36. A method in accordance with claim 35, further comprising:
marking the receptacle with an ID label;
transmitting an identification code from the interrogator unit;
comparing the identification code with the ID label; and
testing the operational circuitry of the integrated circuit in the
receptacle only when the identification code matches the ID label of the
receptacle.
37. A method for testing an integrated circuit including operational
circuitry, comprising:
providing an interrogator unit;
placing the integrated circuit in a receptacle coupled to test interface
circuitry, the receptacle supplying power to the integrated circuit;
optically transmitting interrogating information from an optical
transmitter having an optical communication range contained in the
interrogator unit to the test interface circuitry on the burn-in board;
and
testing the operational circuitry according to the interrogating
information.
38. A method in accordance with claim 37, further comprising heating the
integrated circuit.
39. A burn-in testing system for evaluating a circuit under test,
comprising:
a burn-in board configured to receive and supply electrical power to the
circuit under test;
test interface circuitry configured to be coupled to the circuit under
test, the test interface circuitry including a transmitter and receiver;
and
an interrogator unit having a radio communication range extending to the
test interface circuitry, the interrogator unit being configured to
exchange signals with the circuit under test via radio communication with
the transmitter and receiver.
40. A burn-in testing system in accordance with claim 39, wherein the test
interface circuitry is mounted on the burn-in board.
41. A burn-in testing system in accordance with claim 39, further
comprising a plurality of receptacles on the burn-in board and configured
to receive the circuit under test, and coupled to the test interface
circuitry.
42. A burn-in testing system in accordance with claim 41, further
comprising conductive traces on the burn-in board coupling the receptacles
to the test interface circuitry.
43. A burn-in testing system in accordance with claim 41, further
comprising power conductors supported by the burn-in board, configured to
be coupled to the circuit under test and configured to be coupled to a
power supply to power the circuit under test during burn-in testing, the
power conductors comprising conductive traces formed on the burn-in board.
44. A testing system for evaluating integrated circuits, comprising:
an interrogator unit having a transmitter having a radio communication
range, the interrogator unit being configured to transmit interrogating
information via radio communication;
a receiver configured for communications with the transmitter; and
a burn-in board within the radio communication range, the burn-in board
being configured to support respective individual integrated circuits, the
burn-in board supporting the receiver, the burn-in board having burn-in
test conductors configured to couple the receiver to respective integrated
circuits and to supply electrical power to the integrated circuits.
45. A testing system in accordance with claim 44, further comprising test
interface circuitry supported by the burn-in board, the test interface
circuitry including the receiver.
46. A testing system in accordance with claim 45, the testing system being
configured to perform dynamic testing.
47. A testing system in accordance with claim 45, the testing system being
configured to perform dynamic testing wherein the integrated circuits are
cycled on and off during a period of time greater than twelve hours and
less than thirty-six hours.
48. A testing system in accordance with claim 45, wherein the testing
system includes a burn-in oven and the testing system is configured to
perform dynamic testing wherein the integrated circuits are cycled on and
off during a period of time of at least twelve hours while the burn-in
oven heats the chamber to a temperature greater than 100 degrees Celsius.
49. A testing system in accordance with claim 45, wherein the test
interface circuitry is secured to the burn-in board.
50. A testing system in accordance with claim 45, wherein the testing
system is configured to perform static testing.
51. A testing system in accordance with c | | |