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Description  |
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FIELD OF THE INVENTION
The present invention relates generally to an apparatus and method for
testing logic on circuit chips. In particular, the present invention
relates to structure and function of the test logic within the main logic
of a chip for partial-scan built-in self-test on a circuit chip.
BACKGROUND OF THE INVENTION
The number of devices, also called transistors, on a commonly available
integrated circuit may be very large. Very Large Scale Integrated ("VLSI")
circuits with 15 million devices have been developed. The present trend in
integrated circuit design is toward even higher levels of circuit
integration, thereby reducing costs and improving circuit reliability. As
IC technologies continue to develop, it is expected that circuits with at
least 100,000,000 devices will become common.
Increased circuit integration is not, however, obtained without drawbacks.
Increasing chip testing costs tend to reduce the benefits derived from
more economically efficient design and production techniques. Typically,
the costs associated with integrated circuit chip testing increases more
than the increase in the number of devices thereon. Large expenses are
incurred in the development of computer programs for running test
routines. The engineering effort and computer time needed to devise these
test routines may even exceed the requirements for designing the chip
itself. It is not uncommon to employ as many engineers to develop tests
for an IC to assure the quality of the part as the number of engineers
designing a part.
Depending upon the particular type of circuit involved, circuit chip
testing costs can now account for roughly 10 to 40 percent of the total
manufacturing costs. The most commonly used technique of IC testing is
known as scan design. Scan design requires the circuit designer to break
complex logic circuits into smaller blocks, and to include artificial
pathways into and between the blocks for data transmission. Complex
sequential circuitry is thereby temporarily converted to combinational
circuitry for testing purposes.
Scan design techniques are far from optimal. Scan design does not, in
general, permit faults to be isolated to a particular chip or wire net.
The inclusion of additional test points and transmission paths required
for scan design degrades overall IC performance. Scan design also requires
additional clock circuitry and relatively complicated maintenance
software.
Another testing technique, one that is becoming increasingly popular, is
the built-in self-test technique. As its name implies, built-in self-test,
or BIST, test systems are fabricated on the IC chip to be tested. BIST
systems include a pattern or operand generator for producing test
operands. Each test operand is applied to the IC logic, and the response
thereto analyzed by means of a shift register. The response to thousands,
and even millions, of test operands is then compressed into a "signature",
which is compared to predetermined signatures for a go/no go indication of
the IC's operation. One such BIST system is disclosed in the Van Brunt
U.S. Pat. No. 4,357,703.
The BIST approach to circuit testing offers numerous advantages. BIST has
minimal impact upon main logic functions since it is typically fabricated
on the sparsely used peripheral areas of the integrated circuit chip.
Since test results are processed by the BIST system, the number of tasks
which must be performed by external test equipment is reduced. Specially
developed maintenance software is therefore greatly reduced. Dynamic
testing at full system clock rates significantly reduces system test
times. BIST systems can also be used for testing integrated circuits at
the wafer, chip, and system levels. Since they are independent of specific
chip logic functions, BIST test systems can be used on any number of
different types of circuit chips. The BIST approach also permits IC chips
to be tested after they have been assembled into a computer, even though
they are inaccessible to more traditional maintenance techniques. This
will be the case, for example, when the IC is immersed in a liquid coolant
to increase its performance.
Even though BIST test systems offer many advantages over alternative
techniques, BIST test systems have yet to be developed to their fall
potential. BIST testing systems have significant shortcomings when used in
integrated circuits having 100,000 or more devices. BIST systems usually
generate random numbers as test operands. The quality of many of the test
operands, in terms of stressing the part, may be poor. When an integrated
circuit has a high number of devices or transistors and as the operand
goes deeper and deeper into the logic on the integrated circuit, the test
becomes less and less effective. If there is a defect in the integrated
circuit at a latch in the middle of the integrated circuit, there is a
distinct possibility that the defect may go undetected. Certain areas of
the integrated circuit may be untestable in that a defect may not
propagate through many layers of logic and to an output pin to cause a
test result indicating a defect. The result is that the integrated circuit
may test "good" when it is really a defective part that should be
scrapped.
As a result, there is need for a method and apparatus for determining if a
logic module may have a portion that is untestable. Furthermore, there is
a need for a flexible self-testing method and apparatus that is adaptable
and can be used to sensitize certain paths on an integrated circuit so
that the fault that might otherwise go unnoticed is output to the output
pins. There is also a need for developing a testing method and apparatus
that can be used by the logic designer or logician to add logic during the
design phase to sensitize paths to untestable areas. There is also a need
for developing a testing method and apparatus that can be used by the
logic designer or logician to add logic during the design phase to make a
logic block more testable. There is also a need for a flexible method and
apparatus which can be used to control the test as well as the type of
test that to be executed. Furthermore, there is a need for a method and
apparatus that tests the integrated circuit to the extent necessary to
determine if the part is good or bad. Furthermore, it would be
advantageous if the testing method also could interface with a boundary
scan type test, such as JTAG. JTAG is a boundary scan standard, found at
IEEE/ANSI 1149.1-1990, which is a collection of design rules applied
principally at the integrated circuit level. It would also be advantageous
if the power to the logic used for testing the integrated circuit could be
powered down when the integrated circuit is not under test to save power
and reduce the overall cooling load on the computer. This would lower the
amount of energy used and reduce the costs associated with operating the
computer.
SUMMARY OF THE INVENTION
A digital integrated circuit apparatus includes main logic for performing
logic operations. The main logic is further comprised of a plurality of
logic modules, each having at least one logic block associated with the
logic module. Many times several logic blocks are associated with the
logic modules. A logic module is an internal logic block of an IC under
test. The main logic further also includes a number of input pins for
receiving data and a number of output pins for outputting data from the
main logic. Also included on the integrated circuit apparatus is testing
logic for performing dynamic tests of the main logic. The testing logic
further includes a first type of built-in testing logic for testing a
first number of the logic modules of the main logic and a second type of
built-in test logic for testing a second number of logic blocks. The first
type of built-in testing logic could be logic known as BIST. The second
number of logic blocks connected to the second type of built-in scan logic
are generally untestable using the first type of built-in logic. The
second type of testing logic includes a test data input for inputting test
data to the second type of testing logic and to the input pins of the main
logic, and a test data output for outputting test data from the second
type of testing logic and from the main logic. The second type of built-in
scan logic includes an internal scan ring.
The testing logic also includes a command register for receiving commands
and outputting control signals to control the main logic and the testing
logic. The control signals output from the command register included
generation of data, and shifting of data. One of the commands is for
substantially powering down the testing logic on the logic chip when the
logic chip is not under test.
Advantageously, the invention includes a method and apparatus for
determining if a logic module may have a portion that is untestable and a
method and apparatus for testing the untestable portions. The invention
also provides a method and apparatus that can be used by the logic
designer or logician to add logic during the design phase to sensitize
paths to untestable areas. The invention provides a flexible self-testing
method and apparatus that is adaptable and can be used to sensitize
certain paths on an integrated circuit so that faults that might otherwise
go unnoticed are output to the output pins. The command register of the
invention also provides for flexible control of the test as well as
flexibility in the types of test to be executed. An additional advantage
of the testing method is that it can also could do boundary scan type
testing, much like the JTAG standard, found at IEEE/ANSI 1149.1-1990. The
command register can also power down the logic used for testing the
integrated circuit when the integrated circuit is not under test. This
saves power and reduces the overall cooling load on the computer.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a supercomputer showing the large number
of boards, which are populated with numerous modules which include
integrated circuits contained in a supercomputer.
FIG. 2 is a schematic diagram of a module showing chips and logic blocks
within the module.
FIG. 3 is a block diagram showing several components electrically connected
to one another in accordance with this invention.
FIG. 4 is a schematic diagram of a portion of the logic of the controller
used to control the test logic of this invention.
FIG. 5 is a schematic diagram showing the input cell of this invention.
FIG. 6 is a schematic diagram showing the output cell of this invention.
FIG. 7 is a schematic diagram showing the test cell for bidirectional pin.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
In the following detailed description of the preferred embodiments,
reference is made to the accompanying drawings which form a part hereof,
and in which are shown by way of illustration specific embodiments in
which the invention may be practiced. It is to be understood that other
embodiments may be utilized and structural changes may be made without
departing from the scope of the present invention.
Referring to FIG. 1, a supercomputer 100 is shown. The supercomputer 100
includes a housing 102 which is depicted by dotted lines. The
supercomputer includes a system interconnect board 110. CPU boards 120,
122, 124 and 126 are actual hardware printed circuit boards attached to
the system interconnect board 110. Common memory boards 130, 132, 134, and
136 are also hardware printed circuit boards attached to the system
interconnect board 110. Each of the CPU boards 120, 122, 124 and 126 shown
in FIG. 1 is actually a stack of eight boards. As can be seen, there are
many boards that must undergo testing. If any one of the boards is bad,
the supercomputer 100 is bad. It is advantageous to have a self-testing
capability in the case of any computer and extremely advantageous in a
supercomputer 100 since there are a large number of boards to test. If the
testing had to be done by hand or hook up of external circuitry, testing a
supercomputer would be cumbersome and possibly impossible. In addition, a
supercomputer 100 also has a large number of boards 120, 122, 124, 126,
130, 132, 134, and 136 which require a relatively large amount of power to
operate. Each of the boards 120, 122, 124, 126, 130, 132, 134, and 136 may
include a number of integrated circuits. The boards and integrated
circuits also include a multiplicity of logic modules. Since there are so
many boards and logic modules involved, even a small savings of resources
at the board or module level would be significant.
FIG. 2 shows one hardware printed circuit board 200. The printed circuit
board 200 includes chips 210, 212, 214, and 216. Each of the chips
includes one or more logic blocks or logic modules. For all practical
purposes, each chip includes a plurality of logic blocks or modules. A
logic module is an internal logic block of an integrated circuit. The
logic module is a portion of all the logic associated with an IC or
integrated circuit. A logic module is typically an internal logic block of
an IC being tested. In FIG. 2, chip 210 is the only one illustrated with
logic blocks. Chip 210 includes logic blocks 230,232, 234, and 236.
FIG. 3 is a schematic diagram showing one chip 230. The chip 230 includes a
grouping of logic modules, such as logic module A and logic module X. It
should be understood, that the logic modules discussed with respect to
FIG. 3 may bear no real relation to the hardware shown in FIG. 2. The
hardware shown in FIG. 2 is used to implement the logic in the logic
blocks and logic modules. Chips can be thought of as merely a grouping of
logic modules. The logic modules themselves are groupings of logic that
make sense to a logic designer or logician. For example, logic module A
(reference number 330) shown in FIG. 3 may be the logic for performing a
certain function, such as a vector pipeline. Logic module X (reference
number 340) is the logic associated with another function. The chip 230 of
FIG. 3 includes the self-testing logic in accordance with this invention.
Each logic block includes main or core logic, and testing logic. The main
or core logic typically includes tens or even hundreds of thousands of
electronic devices such as transistors or FETs, and occupies a major
portion of the surface area of the integrated circuit chip. The main or
core logic is the logic that is applied to data by the computer or
information handling system. The testing logic is logic that is used when
a self-test is performed on the particular board or the particular
integrated circuit chip. Part of the self-test function is to load test
data into the main logic of the chip. The testing logic occupies a minor
portion of the surface area of the integrated circuit chip.
FIG. 3 illustrates, for the most part, the testing logic, although the main
or core logic is partly shown in FIG. 3. For example, each logic module
330 and 340 is represented by a bound box. Some of the main or core logic
is within the logic module 330 and 340. Also shown within the bound box of
logic module 330 is a smaller box which is the internal test logic 332.
Similarly, a smaller box representing the internal test logic 342 for
logic module 340 is also shown.
As shown in FIG. 3, the board 120 includes input pins 300 and output pins
302. Data is input to the input pins 300 when the board 120 is not in test
mode. The input pins 300 are electrically connected to the input test
logic 310. The input test logic includes a plurality of input cells, one
of which is shown in FIG. 5. The input test logic 310 is invisible to data
brought in on the input pins 300 when the chip 230 is in normal operation.
The logic module captures boundary scan or other test operands coming in
from the chip's input pins 300 and has several other functions which will
be discussed with respect to FIGS. 4-7. The chip also includes output test
logic 320 which includes a plurality of output cells, one of which is
shown in FIG. 6. The output cells and the output test logic 320 are also
invisible when the chip 230 is in normal operation. The output test logic
320 and the individual output cells in that test logic also must generate
boundary scan or other test operands being driven from a chip's output
pins for when parametric or module level tests are run. Boundary scan
includes input logic (310) and output logic (320). This logic has its
functionality expanded (above boundary scan) to support the other test
functions.
The chip 230 also includes an external boundary scan ring 350. The external
boundary scan ring 350 is attached at one end to the input test logic 310
and the input pins 300, and attached at the other end to the output test
logic 320 and the output pins 302. The chip 230 also has an internal scan
ring or T_Scan ring 360. The internal scan ring 360 is connected to
portions of the main logic which are not otherwise testable by a separate
self-testing algorithm. The internal scan ring 360 is a serial chain to
all of the portions or blocks of logic that need to be tested that are
otherwise untestable using a self-test such as BIST. Generally, when BIST
is run on the logic of a part, at deeper layers of logic, many times a
fault will not be seen or output in response to running a first
self-testing algorithm, such as BIST. The logician or logic designer
determines which portions of logic are not testable using a first type of
self-test and then attaches all the portions of logic that are not
testable such as logic block 332 and logic block 342, in a serial fashion
on an internal scan ring 360. The internal scan ring 360 sensitizes
controls and observes the path to the untestable logic on the chip 230.
The untestable logic in module 330 is depicted as logic block 332 and the
untestable logic in logic module 340 is logic block 342. These logic
blocks are part of a serial chain to all the blocks that need tests.
At the time that the logic blocks are designed by the logic designer or
logician, a software package can be used to test a logic module, such as
330. The logician determines which of the portions of the logic module 330
are untestable using a first type of self-test, such as BIST. In some
cases, logic is added to control some of the main or core logic so that
faults can be observed using the first type of self-testing logic, such as
BIST. In other cases, even if additional test logic is put on the part,
certain blocks of logic, such as 332, cannot be adequately tested using
the first type of internal or self-testing logic. The blocks such as 332,
which cannot be tested using a first type of self-testing logic, are then
attached serially to the internal scan chain 360. Attaching the untestable
logic blocks 332 and 342 to the internal scan chain 360 sensitizes the
path on the part so that a fault that occurs within the logic blocks 330
or 340 would be observable at the output pins or represented in the test
data out signal.
The chip 230 also includes a command register 370. Various commands can be
loaded into the command register including powering up the test logic when
a test logic bit is enabled and performing a boundary scan test and the
shifting of data at various portions of the test logic. The command
register 370 has control outputs 371, 372, 373 and 374. Some of the
outputs, such as 373 and 374, are latched by a control latch 375. The
outputs 371, 372, 373 and 374 control the test logic. The control outputs
371, 372, 373 and 374 control the external boundary scan test on the
external boundary scan ring 350 as well as the first type of internal
self-test, such as BIST, as well as control the logic on the internal scan
ring 360.
The chip 230 also has a test data input ("TDI"), a test master signal
("TMS") and a test clock ("TCK"). The test data input signal is input to
the command register 370 as well as to the internal scan ring 360. The
test data input is placed on the input pins 300 by the command register
360 by controlling the input pin test logic in the input test logic 310.
An input MUX 380 is used after the first loading of test data or the
initialization of the input pins 300. The input MUX has the test data in
as one input and the output of the output test logic 320 as another input.
The output from the output test logic 320 is used or is fed into the input
MUX 380 to randomize the test data input as well as to keep any failure
observed at the output pins 302 within the part. It should be understood
that the self-test runs on a set of randomized numbers that are produced
in successive clock cycles. In other words, the operand or test data in
value is randomized during the self-test mode. Rather than add a random
number generator to the chip 230, a pseudorandom generator is produced by
inputting the test data in and the output of the test logic 320 at the MUX
380. Similarly, the internal scan ring includes a MUX 362 which has as one
of its inputs the test data in, and as another of its inputs, the output
from the end of the internal scan ring 360. By inputting the output of the
scan ring to the MUX 362, a pseudorandomizer of data is generated and in
addition any failure that is produced in the internal scan ring 360 is
kept on the part throughout the test which can be thousands of clock
cycles long. The output of the output test logic 320 and the output of the
internal scan ring 360 are both input to a multiplexer or MUX 390 to
produce the test data output ("TDO"). The test data output is then
checksummed to determine if the chip 230 and the main or core logic
thereon is good.
The advantage of the test logic implementation shown in FIG. 3 in which
there is an external boundary scan ring 350, an internal scan ring 360, as
well as a first type of internal self-testing, is that all of the logic or
core logic on the chip 230 can be adequately tested. Use of the internal
scan ring 360 assures that portions of the logic or logic block, such as
332 and 342, which would not be testable by a first type of internal
self-testing, such as BIST, can also be tested. The amount of test logic
used is just enough to allow for adequate testing of the part. This
minimizes the overhead on the part that is devoted to test logic. It is
said that this is a partial-scan type of self-test. Use of the internal
scan ring 360 assures that the untested portions when a fault results in
an untestable logic block 332 and 342, that the fault will be observed at
the output pins or in the test data out signal. An additional advantage is
that a command register is placed on board the chip 230. This allows for
control outputs that are used to control the test logic on board the chip
230. In addition, the command register has a number of inputs which allows
for flexibility in the type of command that can be input to the command
register.
The command register 370 also allows the flexibility of sending in commands
to the command register that allow for both internal self-testing as well
as external scan testing between the parts. The internal self-testing can
be used to test the main or core logic within the part. The external scan
test can be used to check the connections between the output pins and
input pins of the chip 230 and the actual board upon which it sits. The
internal self-testing and external scan test are done at different times.
In addition, since this is a partial-scan type of test, the overhead
associated with it is relatively inexpensive. In other words, the amount
of test logic used is just enough to provide for adequate testing of the
part or chip 230 and, therefore, the amount of test logic that must be
added to the chip is minimized. Since the amount of test logic is
minimized, the amount of "overhead" is also minimized in that less testing
logic has to be incorporated per chip. An additional advantage is that one
of the bits in the command register 370 controls the powering up or
powering down of substantially all the test logic on board the chip 230.
This also reduces the operating overhead on the chip. For example, main or
core logic on such a chip may dissipate 70 watts while the testing logic
may use 10 watts of power. In previous designs, the test logic was always
powered on and, therefore, the extra heat dissipation had to be dealt with
in terms of cooling the part.
The Command Register
The test control/command register 370 is a serial chain of 18 bits. Each
bit controls one specific function associated with chip testing so that no
decoding is needed. Some of the bits are used directly from the register
while some other bits are forced into another flip-flop that then drives a
fanout. As a result, some functions can remain valid even while data is
changing in the control register. Bit 0 of the register is the bit
immediately against the TDI pin.
A test is performed by loading the control register, with TMS inactive, and
then activating TMS. On the next TCK*Clk edge the control latches and
fanouts are driven with the new data. The `Clk` is the main system/chip
clock signal.
The control register bits are:
Bit # Latch Function
0 Y Power-up all test logic when active..sup.1 Don't have to load
the
whole control register to change this state.
1 -- Boundary Scan Test if active. Gives compatibility with
previous design.
2 -- Enable shift data into all Boundary Scan ("BS") Flip-Flops
("FFs") (Input, Output, Bidirectional) when active.
3 -- Enable input pin data into BS FFs [Exclusive-OR ("XOR")
data if both 2 and 3 active].
4 -- Enable input pin data to chip logic if inactive; enable BS
test data to logic if active/BIST.
5 -- Enable clock to Input BS register when TMS active.
6 -- Enable logic data to Output BS FFs (XOR data if 2 and 6
both active).
7 -- Enable chip data to output pins if inactive; enable Output
BS test data to output pins if active.
8 -- Enable clock to Output BS register when TMS active.
9 -- Enable clock to Bidirectional BS register when TMS active.
10 -- Enable shift of T_Scan internal register when inactive;
enable test function of T_Scan when active.
11 -- Enable clock to T_Scan internal register when TMS active.
12 -- Enable test data to ICM logic if active, otherwise allow
normal data.
13 -- Force `even` Bidirectional outputs on when active..sup.2
14 -- Force `odd` Bidirectional outputs on when active..sup.2
15 Y IZZ Master Clear when active. The control command
that starts a test will (presumably) turn this off, if
used.
16 Y IZU Test Mode if active. Use is up to logic designers.
17 -- IZV Enable test initialization. Use is up to logic
designers. Typically used with IZZ and IZU
as required.
.sup.1 The driver flip-flop should power-up in a clear (off) state if at
all possible.
.sup.2 Master clear of the chip must turn off/disable all bidirectional
outputs if these functions are present.
In addition to the invention, there are two force bits (bits 12 and 13) of
bidirectional pins because the input and output logic levels of those pins
are not compatible with the other pin's levels. This means that, on chip,
only those pins can be jumpered to one another for testing.
There are three functions that control data paths within the test logic.
These functions are associated with the input multiplexer 380 and output
multiplexer 390 in the TDI and TDO paths. The input MUX 380 is controlled
by the TMS signal. If TMS is inactive, the output of the control register
is connected to the first bit of the boundary scan register. If TMS is
active, the last bit of the bit shift ("BS") output register is connected
to the first bit of the BS input register.
The output MUX 390 is controlled by bits 10 and 2 of the control register.
If bit 10 is cleared and bit 2 is set and active (i.e., TMS is enabled),
the T_Scan output is connected to TDO. Otherwise, the last boundary scan
output bit is connected to TDO.
The internal scan ring MUX 362, the input of the T_Scan register, is also
controlled by TMS.
Bit 15 of the command register provides Master Clear/IZZ. This signal is
ORed with the MC input pin if there is such a pin. This signal replaces
the pin of the same name in ECD chips.
Bit 17 of the command register holds Test Initialize/IZV. This signal is
used to initialize logic in test mode. An example is that of forcing a
counter in the address path to generate an address sequence to write each
location of a custom RAM block. This signal should clear the counter,
enable it to count and force the count to the address inputs of the logic
block (or blocks) being initialized. When the signal drops, a normal test
can begin or whatever is indicated by the other control signals.
Another test signal is provided. Sometimes, in order to get sufficient test
coverage, a signal is needed that forces logic a particular way or into a
specific test at regular or pseudorandom intervals. The test controller
provides such a signal, IZX, and its complement izx. These signals are
enabled when both IZU and IZV are act | | |
