A system and method for circuitry design verification testing which provides for maximized code re-use without unnecessary allocation of system resources. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class which collects convenience routines and thereby maximizes code re-use. The system transaction class contains pointers to device transaction classes which correspond to each of the functional models in the simulation subsystem, but does not require instantiation of all of the device transaction classes and associated device objects. One or more configuration transaction classes derived from the system transaction class define transactions between selected ones of the functional models within the simulation subsystem. The configuration transaction classes inherit the convenience routines of the system transaction class, but cause instantiation of the respective functional models only when needed for a transaction.
Configurations of the invention simulate an exchange of calls emanating from a SAN management application to a plurality of manageable entities. The simulated call load provides simultaneous simulated calls for observing and analyzing responses to various loading scenarios characterized by multiple pending calls to the SAN. Configurations discussed herein identify a processing work burden and corresponding completion time associated with each of the simulated calls. A simulation agent aggregates the work burden of concurrent requests and computes a latency factor associated with each call based on the load presented by all pending calls. By adjusting the latency time of each pending call, and adjusting the latency to represent the additional processing imposed by successive pending calls, the simulated responses provide an accurate set of responses, rather than merely returning an unencumbered rapid response of expected content which may elusively represent the actual timeliness of responses in a loaded system.
Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.
