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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring board where on electronic components such as LSI chips are mounted on the surface thereof and, more particularly, to a low-impedance wiring board having an electric element such as a capacitor
incorporated in the wiring board.
2. Description of Related Art
Recently, as telecommunication apparatuses proliferate, electronic equipment operating at a high speed is increasingly used and accordingly demands for electronic packages capable of operating at high speeds are increasing. In order for a high
speed operation, noises on electric signals must be minimized. This requires that passive electronic components such as capacitors be placed in proximity to active electronic components and that the wiring length of electronic circuits be minimized,
thereby to reduce the inductance of the interconnection lines.
For example, Japanese Unexamined Patent Publication (Kokai) No. 7-142871 (1995) proposes that a bypass capacitor is formed between a planar pattern drawn from a power supply layer and a planar pattern drawn from ground layer. In this
constitution, however, electromagnetic field concentrates in a small number of via hole conductors that are connected to a power supply layer formed inside of the wiring board or the planar electrode used to lead from the ground layer. There is also
such a problem that increasing the number of the via hole conductors used in interconnection leads to a decrease in the capacity of the dielectric layer.
Japanese Unexamined Patent Publication (Kokai) No. 10-92966 (1998) proposes that a chip capacitor is mounted near a cavity wherein a semiconductor device is hermetically sealed, whereby the chip capacitor is disposed as near to the semiconductor
device as possible. However, since the capacitor is mounted in portions different from the portion where the semiconductor device is wired, wiring length increases, resulting in increasing value of inductance. That is, connection between the capacitor
and the semiconductor device requires it to make wiring through the via hole conductors and the wiring circuit formed in the dielectric substrate.
In Japanese Unexamined Patent Publication (Kokai) No. 11-220262 (1999), such a wiring board is proposed as all insulation layers that constitute a dielectric substrate are formed from a mixture including an inorganic filler and a thermosetting
resin, in relation to a module incorporating circuit components and a method of producing the same. However, this circuit board has such a problem as the weak mechanical strength and low rigidity of the board cause the wiring board to deform with a flip
chip portion warping, when the semiconductor device is mounted on the surface of the wiring board by flip chip mounting procedure.
Moreover, for example, Japanese Unexamined Patent Publication (Kokai) No. 2-121393 (1990) proposes to embed a chip capacitor in an insulation layer between a power supply layer and a ground layer. In Japanese Unexamined Patent Publication
(Kokai) No. 11-220262 (1999) and Japanese Unexamined Patent Publication (Kokai) No. 10-51150 (1998) such wiring boards are proposed as semiconductor devices and capacitors are incorporated in a dielectric substrate.
In the constitution disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2-121393 (1990), ceramic chip capacitors embedded in an insulation layer between a power supply layer pattern and a ground layer pattern are supported by the
surrounding insulation layers. However, connections between the terminal electrodes of the capacitor, power supply layer in the substrate and the ground layer are made by pressure contact. As a result, when subjected to a thermal shock, the connection
performance between the terminal electrode and the wiring circuit layer changes due to the difference in the thermal expansion coefficient.
Japanese Unexamined Patent Publication (Kokai) No. 11-220262 (1999) also proposes to connect the electrodes of a semiconductor device and a wiring circuit layer by means of a conductor such as gold, silver, copper, nickel or solder. However, in
the case that an electronic component such as semiconductor device is soldered onto the surface of a wiring board, there has been such a problem that the connection performance between the terminal electrode and the wiring circuit layer changes when the
solder is reflowed at a temperature from 220 to 300.degree. C. Where the component incorporated inside is a capacitor, in particular, inductance due to the capacitor increases, thus leading to a change or deterioration of the function of the capacitor
to remove noise.
Moreover, in the capacitor incorporating wiring board of the prior art described in for example, Japanese Unexamined Patent Publication (Kokai) No. 2-121393 (1990), Japanese Unexamined Patent Publication (Kokai) No. 11-220262 (1999) or Japanese
Unexamined Patent Publication (Kokai) No. 10-51150 (1998), there is a problem of low reliability of connection between the capacitor and the wiring circuit layer on the wiring board when thermal cycles or stress is exerted thereon.
Such a method has been proposed for fastening a capacitor on a wiring board that a clearance between the capacitor and an insulation layer is filled with a thermosetting resin and the thermosetting resin is hardened together with the insulation
layer thereby to bond firmly.
However, since the capacitor has lower thermal expansion coefficient than the insulation layer, the capacitor is subjected to stress when thermal cycles are applied. The stress may damage the capacitor or impair the reliability of the connection
thereof with the wiring circuit layer.
In the case of for example, Japanese Unexamined Patent Publication (Kokai) No. 11-220262 (1999), although a constitution of incorporating semiconductor device and/or chip electric components in a wiring board is described, there is no description
on a relation with via hole conductors of the wiring board or the conductor layer where an electric circuit is to be formed, or on the relation between the via hole conductors connected to a plurality of electric components. For example, in the case
that via holes where currents flow in the same direction are located close to each other, the effect of the mutual inductance of the two via hole conductors becomes conspicuous particularly when a signal of high frequency is transmitted, resulting in an
increase in the inductance of the wiring.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a constitution of a wiring board that reduces the generation of noise due to high speed operation of electronic components and effectively decreases the inductance due to electric elements
disposed near an electronic components.
A second object of the present invention is to provide a wiring board that incorporates electric elements such as capacitors inside a dielectric substrate thereof, and ensures excellent performance and reliability of mounting components even in
the case of flip-chip mounting of electronic components such as semiconductor devices on the surface of the substrate.
A third object of the present invention is to provide an electric element incorporating wiring board having excellent reliability of connection between electric elements incorporated inside thereof and a wiring circuit layer formed on the wiring
board.
A fourth object of the present invention is to provide an electric element incorporating wiring board that incorporates electric elements such as capacitors inside a dielectric substrate thereof, and maintains connection between the electric
elements incorporated inside thereof and a wiring circuit layer formed on the wiring board with such an excellent reliability that the functions of the incorporated electric elements does not change after reflow of solder for mounting electronic
components on the surface.
The present inventors have intensively studied about the electric element incorporating wiring board that incorporates electric elements inside an dielectric substrate thereof, and has electronic components mounting surface on the dielectric
substrate, for achieving the objects described above. Consequently, the present inventors arrived at such a constitution as an electric element having at least two first terminal electrodes and at least two second terminal electrodes is used as an
electric element incorporated in a dielectric substrate, a first and a second electrically conductive layer are formed inside of the dielectric substrate disposed between the electric element and the surface of the dielectric substrate, all of the first
terminal electrodes of the electric element are connected to the first conductive layer and all of the second terminal electrodes of the electric element are connected to the second conductive layer, while via hole conductors that penetrate through the
first and the second conductive layers are formed to reach the surface of the dielectric substrate, and the via hole conductors and an electronic component such as semiconductor device mounted on the board surface are electrically connected to each
other.
Thickness of the insulation layer disposed between the conductive layer and the dielectric substrate surface is preferably 0.3 mm or less.
In case a capacitor having two or more positive terminal electrodes and two or more negative terminal electrodes is used as the electric element, for example, the capacitor itself has a low inductance. When connecting the low-inductance
capacitor and the electronic component, the positive terminal electrodes and the negative terminal electrodes of the capacitor are each connected to one of the conductive layers, while the conductive layer and the electronic component are connected
through the via hole conductors. Since the distance between the conductive layer and the electronic component can be decreased by decreasing the thickness of the insulation layer disposed between the conductive layer and the board surface, the
inductance can be effectively reduced.
The dielectric substrate is preferably made in a laminated structure comprising a first insulation layer made of a mixture of a thermosetting resin and an inorganic filler and a second insulation layer made of a fibrous material impregnated with
a thermosetting resin. In this case, it is preferable that the electric element is incorporated in the first insulation layer and the difference in the thermal expansion coefficient between the electric element and the first insulation layer is
7.times.10.sup.-6 /.degree. C. or less. It is also preferable that the second insulation layer is located at the top surface of the dielectric substrate.
Thermal expansion coefficient of the first insulation layer made of the mixture of the thermosetting resin and the inorganic filler can be easily altered by properly selecting the type and quantity of the filler. Thus the thermal expansion
coefficient of the first insulation layer can be easily matched to that of the electric element to be embedded in the first insulation layer. Thus it is made possible to suppress the stress caused by the difference in the thermal expansion coefficient,
and thereby minimizing the deformation of the wiring board and improve the reliability of connection between the wiring circuit layer of the wiring board and the electric element.
On the other hand, when the dielectric substrate is made of only the first insulation layer made of the mixture of the thermosetting resin and the inorganic filler, the substrate has a lower strength as a whole and the surface flatness is likely
to be impaired. Therefore the second insulation layer made of the fibrous material impregnated with the thermosetting resin is stacked on the top or bottom surface of the insulation layer made of the mixture of the thermosetting resin and the inorganic
filler. This increases the strength of the first insulation layer and, at the same time, improves the flatness of the wiring board surface, thereby achieving the wiring board that can be used satisfactorily even when semiconductor devices are mounted by
flip chip bonding.
It is also preferable that terminal electrodes of the electric element and the via hole conductors are directly connected to each other, and the junctions between the terminal electrodes and the via hole conductors include an intermetallic
compound of Cu and Sn. In this case, the via hole conductor preferably includes Cu and Sn as metallic components. Proportion of Sn to the total metal component (Cu+Sn) by weight is preferably in a range from 0.5 to 0.95. Further, an electrically
conductive layer including at least Sn is preferably formed on the top surface of the terminal electrodes of the electric element.
Specifically, a Sn-containing conductive layer is formed on the top surface of the terminal electrodes of the electric element, and the via hole conductors are caused to contain Cu and Sn, and the board is heated to a temperature of 210.degree.
C. or higher. This causes the metallic component based on Cu and Sn included in the via hole conductors and the Sn component of the terminal of the electric element to react with each other, so that intermetallic compounds of Cu and Sn such as Cu.sub.3
Sn or Cu.sub.6 Sn.sub.5 that are excellent in the electrical conductivity and in heat resistance are formed, in addition to Cu and Sn, in the junctions between the via hole conductors and the terminal electrodes of the electric element. As a result,
electrical connection between the via hole conductors and the terminal of the electric element can be improved. Consequently, even when subjected to sudden heating from the outside due to solder reflow or the like, the connection performance between the
terminal electrodes and the via hole conductors does not change. Thus it is made possible to prevent the inductance of the electric element from increasing and achieve stable function.
Reliability of connection can be improved further by making the area of the connecting surface of the terminals of the electric elements with the via hole conductors larger than the sectional area of the via hole conductor.
In the electric element incorporating wiring board described above, the capacitor used as the electrical element can be caused to function as a decoupling capacitor. Thus switching noise generated in the operation of the semiconductor device
mounted on the wiring board can be effectively reduced.
A plurality of capacitors can be incorporated in the electric element incorporating wiring board. In this case, it is preferable to incorporate capacitors of different values of capacitance. This makes it possible for the plurality of
capacitors having different resonant frequencies to function in an integrated form, and results in the capability to achieve low impedance in a wider range and keep the inductance lower over wider frequency band.
In case a plurality of electric elements are incorporated in the dielectric substrate, it is preferable to connect a pair of via hole conductors, that are most proximate to each other between adjacent electric elements, to different conductive
layers among the first and second conductive layers, so that currents flow in different directions in the via hole conductors. Since the mutual inductance of the interconnection including the via hole conductors can be decreased in this configuration,
the electric elements can be mounted with a higher density. A wiring board having a low inductance can be achieved even when the space between a pair of via hole conductors that are most proximate to each other between adjacent electric elements is set
to 0.5 mm or less.
The surface of the electric element other than the first and second terminal electrodes is preferably covered by a thermoplastic resin that has glass transition point not higher than 100.degree. C. This makes it possible to maintain high
reliability of connection between the electric elements and the wiring layer even when the wiring board is subjected to thermal shock due to thermal cycles or solder reflow.
The above objects and other objects, features and effects of the present invention will become more apparent by the description of preferred embodiments that follows with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE
DRAWINGS
FIG. 1 is a sectional view schematically showing an electric element incorporating wiring board according to one embodiment of the present invention.
FIG. 2A is a schematic perspective view of a capacitor used as an example of electric element in one embodiment of the present invention, FIG. 2B shows a pattern of internal electrode for positive electrode thereof, and FIG. 2C shows a pattern of
internal electrode for negative electrode thereof.
FIG. 3A shows a pattern of the first conductive layer formed inside of the wiring board of FIG. 1, and FIG. 3B shows a pattern of the second conductive layer formed inside of the wiring board thereof.
FIGS. 4A to 4D show processes of producing the wiring board of FIG. 1.
FIG. 5 is a sectional view schematically showing an electric element incorporating wiring board according to another embodiment of the present invention.
FIG. 6A is a perspective view showing an example of capacitor that can be incorporated in the wiring board of FIG. 5, and FIG. 6B is a perspective view showing further another example of capacitor.
FIG. 7A is a perspective view showing external terminals of the pair of capacitors incorporated in the wiring board of FIG. 5 and the via hole conductors connected thereto. FIG. 7B shows the state of the via hole conductors being connected to
the pair of adjacent capacitors. FIG. 7C shows the state of connection wherein currents flow through the via hole conductors in the same direction.
FIGS. 8A to 8F are sectional views schematically showing processes of producing the electric element incorporating wiring board of FIG. 5.
FIGS. 9A to 9E are sectional views schematically showing processes of producing the electric element incorporating wiring board according to another embodiment of the present invention.
FIGS. 10A and 10B are sectional views for explaining the structure of the Comparative Example in comparison to the present invention, showing the state of terminal electrodes of a capacitor being connected to via hole conductors.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiment 1
FIG. 1 is a sectional view schematically showing an electric element incorporating wiring board according to one embodiment of the present invention. A wiring board A has a dielectric substrate 1 having a cavity 2 formed inside thereof, and a
capacitor 3 as an example of an electric element incorporated in the cavity 2. Mounted on the surface of the wiring board A right above the capacitor 3 is a semiconductor device 4 as an electronic component.
The capacitor 3 incorporated in the dielectric substrate 1 has at least two positive electrodes and at least two negative electrodes. An example of the capacitor 3 is shown in the schematic perspective view of FIG. 2A. The capacitor 3 of FIG.
2A has a capacitor body 3a of rectangular parallele piped shape formed by laminating ceramic dielectric layers 5 including BaTiO.sub.3 as a major component. Formed on the external surface of the capacitor body 3a are four positive terminal electrodes 6a
and four negative terminal electrodes 6b, indicated by hatches in the drawing, being disposed independently and equally spaced thereon. In the capacitor 3 of FIG. 2A, the negative terminal electrodes 6b are formed at the middle of each side and the
positive terminal electrodes 6a are formed at the corners.
Also formed between the ceramic dielectric layers 5 of the capacitor body 3a are an internal electrode for positive electrode 7a (indicated by hatch) having the pattern shown in FIG. 2B and an internal electrode for negative electrode 7b
(indicated by hatch) having the pattern shown in FIG. 2C that are formed alternately. The internal electrode for positive electrode 7a is electrically connected to the positive terminal electrode 6a and the internal electrode for negative electrode 7b
is electrically connected to the negative terminal electrode 6b at the end faces of the capacitor body 3a.
Formed in the dielectric substrate 1 between the electronic component mounting surface and the capacitor 3 incorporated therein are a first conductive layer 8 and a second conductive layer 9 being insulated from each other. The first conductive
layer 8 is, as shown in the pattern diagram of FIG. 3A, electrically connected to the four positive terminal electrodes 6a of the capacitor 3 through the via hole conductors 10 formed to penetrate through the insulation layer right above the positive
terminal electrodes 6a.
Similarly, the second conductive layer 9 is, as shown in the pattern diagram of FIG. 3B, electrically connected to the four negative terminal electrodes 6b of the capacitor 3 through the via hole conductors 11 formed to penetrate through the
insulation layer right above the negative terminal electrodes 6b.
Formed in the first conductive layer 8 is an aperture 12 wherein an electrical conductor is formed so as not to make contact with the via hole conductors 11 that connect the negative terminal electrode 6b and the second conductive layer 9.
Further formed on the first conductive layer 8 connected with the positive terminal electrodes 6a of the capacitor 3 is a via hole conductor 13 extending to the semiconductor device mounting surface. The via hole conductor 13 is connected with a
positive terminal electrode land 14 provided on the board surface. Similarly formed on the second conductive layer 9 connected with the negative terminal electrodes 6b of the capacitor 3 is a via hole conductor 15 extending to the semiconductor device
mounting surface. The via hole conductor 15 is connected with a negative electrode land 16 provided on the board surface.
Bumps of the semiconductor device 4 mounted on the surface of the dielectric substrate 1 are electrically connected to the positive electrode land 14 and the negative electrode land 16.
According to this embodiment, a capacitor having a plurality of positive electrodes and negative electrodes is used as the capacitor 3 to be incorporated in the wiring board A. This constitution decreases the inductance in comparison to a case of
an ordinary capacitor having one positive electrode and one negative electrode. This is because the electromagnetic field is prevented from concentrating in the electrode.
Thus the constitution of this embodiment is made by, after collecting the plurality of positive terminal electrodes 6a and the negative terminal electrodes 6b of the capacitor 3 through the via hole conductors 10, 11 to the conductive layers 8,
9, the via hole conductors 13, 15 lead from the conductive layers 8, 9, respectively, to the surface of the board. This constitution decreases the inductance in comparison to a case of leading directly from the positive terminal electrodes 6a and the
negative terminal electrodes 6b of the capacitor 2 to the substrate surface by means of the via hole conductors. This is because the electromagnetic field concentrated in the via hole conductors is distributed over the flat conductive layer.
Wiring length between the semiconductor device 4 and the capacitor 3 can be decreased by decreasing the thickness of the insulation layer located above the capacitor 3 in the constitution described above. This decreases the inductance further.
Specifically, the inductance can be decreased effectively by setting the thickness x of the insulation layer formed above the capacitor 3, or the depth of the capacitor 3 from the substrate surface, to 0.3 mm or less.
As shown in FIG. 1, pads 18 are provided on the bottom face side of the capacitor 3 incorporated in the wiring board A, the pads 18 being connected to the terminal electrodes 6 of the capacitor 3 via the via hole conductors 17. The pads 18 can
be connected to the power source.
The dielectric substrate 1 of the capacitor incorporating wiring board may be made of either a sintered ceramic insulation material or an organic insulation material that includes at least an organic resin as the insulating component, as long as
the structure incorporating the capacitor as described above can be formed. However, an organic insulation material that does not need sintering process is preferable in order to form such a structure as the capacitor 3 having a plurality of electrodes
that are formed in advance is embedded in the substrate.
Now a method of producing the capacitor incorporating wiring board wherein the dielectric substrate is made of the organic insulation material described above will be described below.
First, an uncured insulation sheet made of a thermosetting resin such as epoxy resin or polyphenylene ether resin, or made of a mixture of the thermosetting resin and a ceramic powder such as silica or alumina, or a prepreg in uncured state made
of woven fabric or nonwoven fabric of glass fiber or aramid fiber impregnated with a thermosetting resin such as epoxy resin is prepared.
As shown in FIGS. 4A to 4D, a cavity 21 for housing the capacitor is formed by punching or the like in the prepreg 20 (FIG. 4A). Meanwhile via holes 23 are formed in an insulation sheet 22 by laser machining, and the via holes 23 are filled with
an electrically conductive paste that includes a conductive powder such as Cu powder, thereby to form via hole conductors 24 (FIG. 4B). Then a conductive layer 25 is formed on the surface of the insulation sheet 22 (FIG. 4C). The conductive layer 25 is
formed by, for example, adhering a metal foil such as Cu foil or Al foil onto the surface of the insulation sheet, and then carrying out the processes of application of a resist, exposure to light, development, etching and removal of the resist thereby
forming a predetermined pattern. Alternatively, the conductive layer 25 may also be formed by transferring a conductive layer of the predetermined pattern, that is formed similarly to the above by adhering a metal foil on the surface of a resin film,
onto the surface of the insulation sheet. Among these, the latter method is preferable because the insulation sheet is not exposed to an etching solution and therefore does not deteriorate.
Then a capacitor 26 is placed in the cavity of the prepreg 20, and insulation sheets 30a, 30b, 30c, 30d, 30e, that have pads 29 for the connection with the via hole conductors 27, the conductive layer 28 and a semiconductor device formed thereon,
are laminated on top and bottom of the prepreg 20 by applying the production process described above (FIG. 4B, FIG. 4C). The laminate is heated to a temperature that is high enough to harden the thermosetting resin included in the insulation sheet and
in the prepreg, thereby to produce the wiring board having the capacitor incorporated therein as shown in FIG. 1.
In order to make reliable electrical connection between the positive and the negative electrodes of the capacitor 26 mounted in the prepreg 20 and the via hole conductors of the insulation sheet, it is preferable to apply a solder, that can be
melted at the thermal setting temperature, onto the junction between the via hole conductors and the capacitor and/or the surfaces of the positive electrode and the negative electrode of the capacitor.
Embodiment 2
Now second embodiment of the present invention will be described below with reference to FIG. 1 to FIGS.4A-4D. Since the second embodiment is similar to the first embodiment described above, description that follows will center around the
difference from the first embodiment while minimizing repeated description.
In this embodiment, the dielectric substrate 1 of the wiring board A comprises a first insulation layer la (hereinafter referred to simply as CPC layer) having a portion made of a mixture of a thermosetting resin and an inorganic filler for
housing the capacitor 3. Second insulation layer 1b (hereinafter referred to as prepreg) made by impregnating at least one layer of fabric with the thermosetting resin is laminated on the front surface of the dielectric substrate 1 whereon the
semiconductor device 1 is to be mounted and/or the back surface whereon connection terminals such as solder ball pads or connecting pins are to be provided.
CPC Layer
The CPC layer 1a where the capacitor 3 is to be embedded is made of a composite material consisting of the thermosetting resin and the inorganic filler. For the inorganic filler, for example, at least one kind of material selected from
SiO.sub.2, Al.sub.2 O.sub.3, AlN and Si.sub.3 N.sub.4 may be preferably used. The inorganic filler is preferably included in a proportion of 35 to 70% by volume with respect to the thermosetting resin. Mean particle size of the inorganic filler is most
preferably in a range from 1.0 to 20 .mu.m. The CPC layer has thickness in a range from 50 to 150 .mu.m per layer, and is formed to a predetermined thickness by laminating a proper number of layers in accordance to the size of the electric element such
as capacitor to be incorporated.
The CPC layer is preferably made to have difference in the thermal expansion coefficient from the electric element to be embedded not larger than 7.times.10.sup.-6 /.degree. C. in a temperature range from -65 to 250.degree. C., particularly not
larger than 5.5.times.10.sup.-6 /.degree. C. When there is a large difference in the thermal expansion coefficient, an intense stress is generated to cause the wiring board to deform. This makes flip chip mounting difficult to carry out, and makes the
connection between the electric element and the wiring layer of the wiring board unreliable, resulting in a possibility that the electric element cannot function properly.
Prepreg Layer
The prepreg layer 1b is made of a fabric impregnated with the thermosetting resin. Thickness of one layer is about 150 .mu.m or less, including 40 to 60% by volume of the fabric and 60 to 40% by volume of the thermosetting resin.
The fabric is made of at least one kind selected from a group of glass and aramid resin. Diameter of the fiber is preferably 10 .mu.m or less in order to ensure mechanical strength.
While the fiber may be distributed uniformly, it is preferably made in the form of woven fabric or nonwoven fabric in order to ensure rigidity of the substrate.
For the thermosetting resin included in the CPC layer and the prepreg layer, at least one kind selected from APP (allylated polyphenylene ether) resin, epoxy resin and cyanate resin is preferably used. The APP resin is particularly preferred for
the low relative dielectric constant, low dielectric loss, low water absorption and high heat resistance due to a high glass transition point thereof. The mixture may also include a dispersant and/or coupling agent in order to improve the wettability
with the filler.
The first conductive layer 8 and the second conductive layer 9 are formed on the prepreg layer 1b disposed between the capacitor 3 and the electronic component mounting surface.
Production Process
For producing the electric element incorporating wiring board of this embodiment, an insulation sheet in uncured state made of a mixture of a thermosetting resin such as epoxy resin or polyphenylene ether resin and a ceramic powder such as silica
or alumina is fabricated as an insulation sheet for forming the CPC layer. As the prepreg layer insulating sheet, an insulation sheet in uncured state made by impregnating woven fabric or nonwoven fabric of glass fiber or aramid fiber with a
thermosetting resin such as epoxy resin is fabricated.
Then the electric element incorporating wiring board is produced through processes similar to the production processes of the first embodiment shown in FIGS.4A to 4D. However, the prepreg 20 is replaced with the CPC layer insulation sheet and
the prepreg layer insulating sheet is used for the insulation sheets 22, 30a, 30b, 30c, 30d, 30e.
Embodiment 3
Now the third embodiment of the present invention will be described below with reference to FIG. 1 to FIGS. 4A-4D. Since the third embodiment is similar to the first embodiment described above, description that follows will center around the
difference from the first embodiment while minimizing repeated description.
This embodiment is characterized in that an intermetallic compound of Cu and Sn is caused to exist at least in the junctions 10a, 11a (FIG.1) between the positive terminal electrodes 6a and the negative terminal electrodes 6b of the capacitor 3
in the wiring board A and the via hole conductors 10, 11 that are connected directly with the former. The intermetallic compound has a high heat resistance and a high electrical conductivity. Consequently, even when subjected to thermal cycles applied
from the outside, connection between the terminal electrodes 6a, 6b of the capacitor 3 and the via hole conductors 10, 11 can be maintained firmly. The intermetallic compound of Cu and Sn may be Cu.sub.3 Sn that includes copper (Cu) and tin (Sn) in the
proportion of 3:1 or Cu.sub.6 Sn.sub.5 with the proportion of 6:5.
When at least Cu.sub.3 Sn that includes copper in higher proportion is included, higher heat resistance and higher electrical conductivity can be given to the via hole conductors. It is particularly desirable that the intermetallic compound
includes Cu.sub.3 Sn or both Cu.sub.3 Sn and Cu.sub.6 Sn.sub.5. More specifically, peak height H1 of Cu.sub.3 Sn located near 2.theta.=57.5.degree. and peak height H2 of Cu.sub.6 Sn.sub.5 located near 2.theta.=60.degree., measured in X ray diffraction
analysis of the via hole conductors 10, 11 satisfy such a relation of inequality as the ratio H1/H2 is 0.5 or higher, especially 1.0 or higher.
It suffices that the intermetallic compound exists at least in the junctions between the terminal electrodes 6a, 6b of the capacitor 3 and the via hole conductors 10, 11. It is particularly preferable that the intermetallic compound exists in
the via hole conductors 10, 11 including the junctions. This not only improves the reliability of connection between the via hole conductors 10, 11 and the terminal electrodes 6a, 6b but also improves the heat resistance and electrical conductivity of
the via hole conductors 10, 11. Thus it is made possible to improve the stability of connection between the terminal electrodes 6a, 6b of the capacitor 3 and other circuits through the via hole conductors 10, 11.
In order to produce the intermetallic compound, it is desirable that at least the junctions of the via hole conductors 10, 11 with the terminal electrodes 6a, 6b include Cu and Sn as metal components. In this case, proportion of copper (Cu) and
tin (Sn) contents is desirably such that weight ratio Sn/(Cu+Sn) is in a range from 0.5 to 0.95. It is also desirable for the reason described previously, that Cu and Sn of the proportions described above are included in the entire via hole conductors
10, 11. Moreover, in order to promote the generation of Cu.sub.3 Sn, weight ratio Sn/(Cu+Sn) is preferably in a range from 0.5 to 0.75, particularly from 0.5 to 0.70, and more preferably from 0.5 to 0.65.
When the weight proportion is less than 0.5, less amount of intermetallic compound is generated which results in lower connectivity between powder particles including copper and between the copper-containing powder and the terminal electrodes of
the capacitor. This leads lower electrical conductivity with the semiconductor device mounted on the surface through the via hole conductors and with the mother board. Moreover, the contact state between metal powder particles and between the via hole
conductors and the terminal electrodes of the capacitor can easily change, resulting in lower electrical conductivity therebetween, in the case of solder reflow particularly at a temperature in a range from 240 to 260.degree. C.
When the weight proportion is higher than 0.95, copper content decreases and therefore less amount of the intermetallic compound is produced. In addition, tin atoms that have not react with Cu to form the intermetallic compound remain unchanged
or form a tin alloy of low melting point. As a result, heat resistance tends to deteriorate during solder reflow (240 to 260.degree. C.), with the unreacted tin and the tin alloy of low melting point melt during solder reflow. Consequently, the
contact state between metal powder particles and between the via hole conductors and the terminal electrodes of the capacitor can easily change resulting in lower electrical conductivity therebetween.
The via hole conductor may also include a thermosetting resin such as epoxy resin, phenol resin and unsaturated polyester resin, or cellulose.
Capacitor Electrodes
In order to improve the connection with the via hole conductors 10, 11 including Cu and Sn as the metal component, it is desirable that there is a conductive layer that includes at least Sn formed on the top surface of the terminal electrodes 6a,
6b of the electric elements such as capacitor 3. It is particularly desirable to form a conductive layer which includes at least one kind of Cu or Ni and a conductive layer which includes at least Sn on the surface of the former conductive layer.
Specifically, the terminal electrodes 6a, 6b of the capacitor 3 are formed as follows. First, electrolytic copper powder having mean particle size of 1 to 5 .mu.m and frit glass powder made of SiO.sub.2, Bi.sub.2 O.sub.3, Al.sub.2 O.sub.3, ZnO
or the like having mean particle size of 3 to 8 .mu.m are prepared. A conductive paste is made by mixing the frit glass powder with ethyl cellulose or acrylic binder. The conductive paste is applied to cover the internal electrode exposed on the end
face of the capacitor, and is fired at a temperature in a range from 800 to 900.degree. C. Thus a electrode layer having a thickness of 3.0 to 15 .mu.m is formed.
Then a Ni film 1 to 5 .mu.m thick and an Sn film 0.5 to 3 .mu.m thick are formed by electroplating on the surface of the electrode layer.
When the conductive layer including Sn is formed on the surfaces of the terminal electrodes 6a, 6b, generation of Cu--Sn intermetallic compound in the junction with the via hole conductors that include at least Cu and Sn can be promoted.
The Cu--Sn intermetallic compound generated in the junctions of the via hole conductors 10, 11 and the terminal electrodes 6a, 6b ensures excellent electrical conductivity. To be specific, after heat resistance test of keeping the temperature at
260.degree. C. for two minutes, resistivity of the junction between the via hole conductors 10, 11 and the capacitor can be kept within 1.times.10.sup.-4 .OMEGA..multidot.cm, or even within 5.times.10.sup.-5 .OMEGA..multidot.cm.
When producing the electric element incorporating wiring board of this embodiment, a conductive paste that forms the via hole conductors is made as follows in order to produce the Cu--Sn intermetallic compound in the junction with the capacitor.
First, copper-containing powder such as copper powder, copper powder covered by silver powder or copper-silver alloy powder is mixed with tin powder or alloy powder made from Sn--Ag--Cu--Bi. Mix proportion of copper (Cu) and tin (Sn) contents is set so
that weight ratio Sn/(Cu+Sn) is in a range from 0.5 to 0.95. 1 to 6 parts by weight of resin and 1 to 4 weight parts of solvent are added to 100 parts by weight of the metallic component.
For the copper-containing powder, it is most desirable to use electrolytic copper powder that has excellent conductivity and good dispersibility with the mean particle size being desirably in a range from 0.5 to 5 .mu.m. When the mean particle
size is less than 0.5 .mu.m, the surface is oxidized resulting in lower conductivity. When the mean particle size is larger than 5 .mu.m, filling ratio of the powder in the via hole conductor decreases, resulting in higher resistivity.
Mean particle size of the tin powder or tin alloy powder is preferably in a range from 1 to 15 .mu.m. When the mean particle size is less than 1 .mu.m, the surface is oxidized result | | |
