High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes

Claims

What is claimed is:

1. A memory system capable of selectively operating in chip-kill mode and non-chip-kill mode, comprising:

a memory controller, a plurality of memory devices, a channel including a data bus connecting the memory controller and the plurality of memory devices;

the memory system comprising circuitry to determine whether the memory system is operating in non-chip-kill mode or in chip-kill mode;

the memory controller comprising circuitry to generate a Read command to the plurality of memory devices via the channel;

in response to the Read command, upon a determination that the memory system is operating in non-chip-kill mode, at least one of the plurality of memory devices returns a first data block to the memory controller via the data bus during a first time period; and,

in response to the Read command, upon a determination that the memory system is operating in chip-kill mode, each one of the plurality of memory devices returns a second data block, smaller than the first data block, to the memory controller via the data bus during a second time period within the first time period.

2. The memory system of claim 1, wherein the first data block forms a data packet returned to the memory controller during the first time period; and

wherein a combination of second data blocks returned to the memory controller by the plurality of memory devices during the first time period forms the data packet.

3. The memory system of claim 2, wherein the first time period comprises a number of clock cycles and the second time period comprises a half clock cycle.

4. The memory system of claim 3, wherein the first data block comprises at least sixteen bytes of data and the second data block comprises at least two bytes of data.

5. The memory system of claim 2, wherein the data bus comprises a first set of data lines and a second set of data lines, and

when the memory system is operating in non-chip-kill mode, the at least one memory device returns to the memory controller one byte of data on the first set of data lines and another byte of data on the second set of data lines during each second period of time in the first period of time; and

when the memory system is operating in chip-kill mode, each one of the plurality of memory devices returns to the memory controller one byte of data on the first set of data lines and another byte of data on the second set of data lines during a selected half clock cycle in the first period of time.

6. The memory system of claim 2, wherein at least one of the second data blocks comprises syndrome data, and wherein the memory controller further comprises an error correcting code (ECC) generator responsive to the syndrome data to detect at least one data error in the data packet.

7. The memory system of claim 6, wherein each second data block contains syndrome data, and wherein the ECC generator is responsive to the syndrome data from the second data blocks to detect at least one data error in the data packet, the ECC generator further comprising circuitry to determine at least one of the plurality of memory devices providing a second data block containing the detected at least one data error.

8. The memory system of claim 7, wherein the memory system further comprises:

a spare memory device; and

circuitry to replace the at least one of the plurality of memory devices providing a second data block containing the detected at least one error with the spare memory device.

9. A method of selectively providing a non-chip-kill mode and a chip-kill mode of operation in a memory system comprising a memory controller, memory devices, and a channel comprising a control/address bus connecting the memory controller and the memory devices, and a data bus connecting the memory controller and the memory devices, the method comprising:

upon determining that the memory system is operating in non-chip-kill mode, generating a Read command in the memory controller, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command returning to the memory controller a first data block from at least one of the memory devices during a first time period; and

upon determining that the memory system is operating in chip-kill mode, generating a Read command in the memory controller, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command returning a second data block from each one of a plurality of the memory devices during the first time period.

10. The method of claim 9, further comprising:

when operating in non-chip-kill mode, receiving the first data block at the memory controller as a data packet during the first time period; and,

when operating in chip-kill mode, receiving at the memory controller a second data block from each one of the plurality of memory devices during the first time period, and combining the received second data blocks into the data packet.

11. The method of claim 10, wherein the memory controller sequentially receives a second data block from each one of the plurality of memory device during a second time period in the first time period.

12. The method of claim 11, wherein the first time period is equal to a number of clock cycles in the memory system and the second time period equals a half clock cycle.

13. The method claim of claim 11, wherein the memory system further comprises an error correcting code (ECC) generator, and wherein at least one of the second data blocks returned from the plurality of memory devices comprises syndrome data, the method further comprising:

evaluating the syndrome data in the ECC generator to detect at least one error, if present, in the data packet.

14. The method of claim 11, wherein the memory system further comprises an error correcting code (ECC) generator, and wherein each second data block comprises syndrome data, the method further comprising:

evaluating the syndrome data in the ECC generator to determining whether a data error exists; and,

upon determining that a data error exists, correcting the data error.

15. The method of claim 11, wherein the memory system further comprises an error correcting code (ECC) generator and a spare memory device, and wherein at least one of the second data blocks comprises syndrome data, the method further comprising:

evaluating the syndrome data in the ECC generator to determining whether at least one data error exists, and which second data block contained the at one data error; and,

replacing the memory device providing the second data block containing the at least one data error with the spare memory device in the event that the at least one data error comprises at least two data errors.

16. A memory system capable of selectively operating in non-chip-kill and chip-kill modes, comprising a memory controller, a plurality of memory devices, and a channel connecting the memory controller and the plurality of memory devices; each memory device comprising:

a memory core having an array of memory locations arranged in columns and rows;

a column decoder addressing the columns, and a row decoder addressing the rows, the column and row decoders cooperating to select memory locations in the memory core;

a plurality of input/output (I/O) amplifiers, each I/O amplifier being associated with a column;

a CAS timing generator providing an I/O amplifier enable signal to the plurality of I/O amplifiers to selectively control data transfer flow from the memory core to the channel;

the memory system further comprising:

a chip kill control circuit and a chip kill decoder;

wherein the chip kill control circuit receives at least a portion of a command packet from the memory controller via the channel, and in response thereto provides a chip kill decoder control signal to the chip kill decoder;

wherein the chip kill decoder, upon receiving the chip kill decoder control signal and upon receiving a chip kill enable signal indicating that the memory system is operating in chip-kill mode, communicates a control signal to the CAS timing generator, whereupon the CAS timing generator defines the I/O amplifier enable signal in response to the control signal.

17. The memory system of claim 16, wherein the chip kill control circuit also provides a chip kill enable signal to the chip kill decoder.

18. The memory system of claim 16, wherein the chip kill control circuit comprises logic implementing a transmission cycle control map, any one selection from the transmission cycle control map defining the chip kill decoder control signal.

19. The memory system of claim 18, wherein the chip kill control circuit also receives a device identification (ID) signal, such that the device ID signal and the portion of the command packet are used to address a selection from the transmission cycle control map.

20. The memory system of claim 19, wherein the plurality of memory devices activates in response to a first portion of the first device ID field, and a second portion of the first device ID field is used to perform sub-page referencing within the plurality of memory devices.

21. The memory system of claim 16, wherein the memory controller communicates a ROW packet and a COL packet to the plurality of memory devices via the channel as part of a data transfer operation, the ROW packet comprising a first device identification (ID) field, and the COL packet comprising a second device identification (ID) field;

wherein the chip kill control circuit receives at least a portion of the second device ID field, and uses the portion of the second device ID field to generate a chip kill decoder control signal.

22. A memory system capable of selectively operating in chip-kill mode and non-chip-kill mode, comprising:

a memory controller, memory devices, and a channel comprising an address/control bus connecting the memory controller and the memory devices, and a data bus comprising a plurality of data lines connecting the memory controller and the memory devices;

the memory system comprising circuitry to determine whether the memory system is operating in non-chip-kill mode or in chip-kill mode;

the memory controller further comprising circuitry to generate a Read command and transmit the Read command to at least a plurality of the memory devices via the address/control bus;

in response to the Read command, upon a determination that the memory system is operating in non-chip-kill mode, at least one of the plurality of memory devices returns a first data block to the memory controller via the data bus during a first period of time; and,

in response to the Read command, upon a determination that the memory system is operating in chip-kill mode, each one of the plurality of memory devices simultaneously returns a second data block to the memory controller via at least one dedicated data bus line during the first period of time.

23. The memory system of claim 22, wherein the first data block comprises a data packet returned to the memory controller during the first time period; and

wherein a combination of the second data blocks returned by the plurality of memory devices during the first time period comprises the data packet.

24. The memory system of claim 23, wherein at least one of the second data blocks comprises syndrome data, and the memory system further comprises an error correcting code (ECC) generator responsive to the syndrome data to perform an error detection algorithm on at least a portion of the data packet.

25. The memory system of claim 24, wherein each one of the second data blocks comprises syndrome data, and the memory system further comprises an error correcting code (ECC) generator, and a spare memory device;

wherein the ECC generator performs an error detection algorithm using syndrome data from each second data block to determine if at least one data error is present in each second data block;

upon determining that a second data block includes one data error, correcting the one data; and,

upon determining that a second data block includes more than one data error, replacing the memory device providing the second data block containing the more than one error with the spare memory device.

26. A method of selectively providing a non-chip-kill mode and a chip-kill mode of operation in a memory system comprising a memory controller, memory devices, and a channel comprising a control/address bus connecting the memory controller and the memory devices, and a data bus comprising a plurality of data bus lines connecting the memory controller and the memory devices, the method comprising:

upon determining that the memory system is operating in non-chip-kill mode, generating a Read command, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command returning to the memory controller a first data block from at least one of the memory devices via the data bus during a first time period; and

upon determining that the memory system is operating in chip-kill mode, generating a Read command in the memory controller, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command returning a second data block from each one of a plurality of the memory devices via at least one dedicated data bus line during the first time period.

27. The method of claim 26, further comprising:

when operating in non-chip-kill mode, receiving the first data block at the memory controller as a data packet during the first time period; and,

when operating in chip-kill mode, receiving at the memory controller a second data block from each one of the plurality of memory devices during the first time period, and combining the received second data blocks into the data packet.

28. The method of claim 27, wherein the first time period is equal to a number of clock cycles in the memory system and the second time period equals a half clock cycle.

29. The method claim of claim 27, wherein the memory system further comprises an error correcting code (ECC) generator, and wherein at least one of the second data blocks returned from the memory devices comprises syndrome data, the method further comprising:

evaluating the syndrome data in the ECC generator to detect at least one error, if present, in the data packet.

30. The method of claim 27, wherein the memory system further comprises an error correcting code (ECC) generator, and wherein each one of the second data blocks comprises syndrome data, the method further comprising:

evaluating the syndrome data in each second data block in the ECC generator;

determining whether each second data block contains a data error; and,

upon determining that a second data block contains an error, correcting the error.

31. The method of claim 27, wherein the memory system further comprises an error correcting code (ECC) generator and a spare memory device, and wherein at least one of the second data blocks comprises syndrome data, the method further comprising:

evaluating the syndrome data to determine whether at least one error is present in the data packet;

upon detecting the at least one data error, determining which second data block contains the at least one data error;

upon determining that the at least one data error comprises one data error, correcting the data error; and,

upon determining that the at least one data error comprises more than one data error, replacing the memory device providing the second data block containing the more than one error with the spare memory device.

32. A memory system capable of selectively operating in chip-kill mode and non-chip-kill mode, comprising:

a memory controller, memory devices, and a channel comprising an address/control bus connecting the memory controller and the memory devices, and a data bus comprising a plurality of data lines connecting the memory controller and the memory devices;

the memory system comprising circuitry to determine whether the memory system is operating in non-chip-kill mode or in chip-kill mode;

the memory controller further comprising circuitry to generate a Read command and transmit the Read command to the memory devices via the address/control bus;

in response to the Read command, upon a determination that the memory system is operating in non-chip-kill mode, at least one of the memory devices returns a first data block to the memory controller via the data bus during a first period of time; and,

in response to the Read command, upon a determination that the memory system is operating in chip-kill mode, each one of a plurality of the memory devices simultaneously returns a second data block to the memory controller via at least a selected one data bus line during each second time period in the first period of time.

33. The memory system of claim 32, wherein the first period of time comprises a sequence of second time periods, and wherein the at least selected one data bus line changes with each second time period in the sequence of second time periods.

34. The memory system of claim 33, wherein the first data block comprises a data packet returned to the memory controller during the first time period; and

wherein a combination of the second data blocks returned by the plurality of memory devices during the sequence of second time periods comprises the data packet.

35. The memory system of claim 32, wherein at least one of the second data blocks comprises syndrome data, and the memory system further comprises an error correcting code (ECC) generator responsive to the syndrome data to perform an error detection algorithm on the data packet.

36. A method of selectively providing a non-chip-kill mode and a chip-kill mode of operation in a memory system comprising a memory controller, memory devices, and a channel comprising a control/address bus connecting the memory controller and the memory devices, and a data bus comprising a plurality of data bus lines connecting the memory controller and the memory devices, the method comprising:

upon determining that the memory system is operating in non-chip-kill mode, generating a Read command, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command returning to the memory controller a first data block from at least one of the memory devices via the data bus during a first time period, wherein the first time period comprises a plurality of second time periods;

upon determining that the memory system is operating in chip-kill mode, generating a Read command, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command, each one of a plurality of the memory devices returns a second data block to the memory controller via a selected data bus line every second time period during the first time period.

37. The memory system of claim 36, wherein the selected one data bus line changes each second time period.

38. A memory system capable of selectively operating in non-chip-kill mode and chip-kill mode, comprising:

a memory controller, memory devices, and a channel comprising a control/address bus connecting the memory controller and the memory devices, and a data bus connecting the memory controller and the memory devices;

wherein the memory controller generates a Read command and transmits the Read command to the memory devices via the control/address bus, the Read command comprising at least a ROW packet and a COL packet, such that;

while operating in non-chip-kill mode the ROW packet activates one of the memory devices, and the COL packet causes a first data block to be read from the activated memory device during a first time period; and,

while operating in chip-kill mode the ROW packet activates a plurality of the memory devices, and the COL packet causes a second data block to be read from each one of the activated plurality of memory devices during the first time period.

39. The memory system of claim 38, wherein the first time period comprises a plurality of second time periods, such that in response to the COL packet one of the activated plurality of memory devices has a second block of data read therefrom during each second time period.

40. The memory system of claim 38, wherein the first data block comprises a data packet, and wherein a combination of the second data blocks read from the activated plurality of memory devices during the first time period comprises the data packet.

41. The memory system of claim 38, wherein the ROW packet comprises a first device identification (ID) field, such that

while the memory system is operating in non-chip-kill mode, the first device ID field provides a unique activation code for the one memory device, and

while the memory system is operating in chip-kill mode, a first portion of the first device ID field provides an common activation code for the plurality of memory devices.

42. The memory system of claim 41, wherein each one of the memory devices is arranged in a plurality of sub-pages, and wherein a second portion of the first device ID field performs sub-page referencing for the activated plurality of memory devices while the memory system is operating in chip-kill mode.

43. The memory system of claim 41, wherein a second portion of the first device ID field comprises error correction data for the ROW packet.

44. The memory system of claim 43, wherein the error correction data comprises one or more parity check bits for the ROW packet.

45. The memory system of claim 41, wherein the COL packet comprises a second device ID field, such that

while the memory system is operating in non-chip-kill mode, data is read from the one activated memory device in accordance with the second device ID field; and,

while the memory system is operating in chip-kill mode, data is read from the plurality of activated memory devices in accordance with a first portion of the second device ID field.

46. The memory system of claim 45, further comprising a chip kill control circuit associated with each memory device, such that

while the memory system is operating in chip kill mode, a second portion of the second device ID field is applied to a chip kill control circuit decoder associated with each one of the activated plurality of memory devices;

wherein the chip kill control circuit generates a control signal defining from which one of the plurality of activated memory devices a second data block will be read for each second time period in the first time period.

47. The memory system of claim 46, wherein the control/address bus and the data bus each comprise multiple wires;

wherein a logic 0 within the memory system is defined by a terminal voltage on any one of the multiple wires; and,

wherein the memory controller and each one of the memory devices assert a logic 1 within the memory system by sinking current from any one of the multiple wires using an open-drain NMOS transistor structure.

48. The memory system of claim 47, wherein during each second time period in which an activated memory device does not have a second block of data read therefrom in accordance with the control signal, that activated memory device outputs all logic 0's onto the data bus.

49. The memory system of claim 45, wherein the chip kill control circuit comprises logic defining a transmission cycle map, any one selection from the transmission cycle map defining the control signal.

50. The memory system of claim 49, wherein a transmission cycle map selection is made in accordance with the second portion of the second device ID field and in accordance with a device activation code common to the plurality of activated memory devices.

51. The memory system of claim 45, wherein each one of the plurality of activated memory devices internally generates a byte read mask in response to the control signal.

FIELD OF THE INVENTION

A memory system characterized by high speed data throughput on a bus between a memory controller and an associated plurality of memory devices is disclosed, wherein the memory system is capable of selectively operating in non-chip-kill and chip-kill modes. A method of selectively operating the memory system is either non-chip-kill or chip-kill modes is also disclosed.

BACKGROUND OF THE INVENTION

During the last several decades, memory technology has progressed dramatically. The density of commercial memory devices, taking Dynamic Random Access Memory (DRAM) as a convenient example, has increased from 1 Kbit to 64 Mbits per chip, a factor of 64,000. Unfortunately, memory device performance has not kept pace with increasing memory device densities. In fact, memory device access times during the same time period have only improved by a factor of 5. By comparison, during the past twenty years, microprocessor performance has increased by several orders of magnitude. This growing disparity between the speed of microprocessors and that of memory devices has forced memory system designers to create a variety of complicated and expensive hierarchical memory techniques, such as Static Random Access Memory (SRAM) caches and parallel DRAM arrays. Further, now that computer system users increasingly demand high performance graphics and other memory hungry applications, memory systems often rely on expensive frame buffers to provide the necessary data bandwidth. Increasing memory device densities satisfy the overall quantitative demand for data with fewer chips but the problem of effectively accessing data at peak microprocessor speeds remains.

Overlaying the problem of data access speed, some computer systems have particularly high requirements for availability and reliability. Central data processing systems at banks and financial institutions, Internet service providers, and telecommunications control systems are ready examples of computer systems which simply can not fail when accessed by a user. The inevitable occurrence of memory device failures within such computer systems has lead to the development of numerous methods and features whereby memory device failures are detected and corrected without shutting down the computer system. One such method is called "chip-kill."

Conventional chip-kill will be explained with reference to FIG. 1. FIG. 1 illustrates a conventional memory system with the architectural changes required to implement chip-kill. In FIG. 1, four memory devices 10 are arranged along a data bus 12. In the example, each memory device is a Dual In-Line Memory Module (DIMM) including 18 DRAMs, each DRAM communicating 4 data bits to/from data bus 12 (i.e., 18.times.4 DRAMs). For clarity, only the data line connections for a single DRAM are shown. This example assumes four (4) groups of 72 bits each (of which 64 bits are data to be returned to the requestor and 8 bits are used for error correction) are communicated by the memory system, thus transferring 256 bits of data to a requester, normally a controller or microprocessor connected to the memory system. Notably, in the conventional chip-kill memory system two quantities of data are returned by each memory device during a read operation: (i) 16 bytes of data to be returned to the requester, and (ii) an 2 additional bytes of data used for error detection and correction. These additional 2 bytes of data are called "syndrome."

Syndrome is used in error detection and correction algorithms to determine whether data from a given memory device contains one or more errors. Some algorithms merely detect the presence of data error(s). Other algorithms have the ability to actually correct one or more detected errors. Single-error-correct/double-error-detect (SECDED) algorithms are well understood by those of ordinary skill in the art. Many other conventional error detection and correction algorithms are known, but as a rule the requirement for additional bits of syndrome increases with the increasing sophistication of the algorithm, i.e., the ability of an algorithm to detect and correct data errors depends on the quantity of associated syndrome provided. For one type of SECDED algorithm, the relationship between data and associated syndrome is well known: the number of syndrome bits increases as the log of the number of data bits. So, 64 bits of data require 8 bits of syndrome, 128 bits of data require 9 bits of syndrome, 256 bits of data require 10 bits of syndrome, etc.

Returning to FIG. 1, each of the four memory device returns 18 bits of data. Thus, 288 bits (256 bits of data and 32 bits of syndrome) are actually read during a read operation. In the example, 8 bits of syndrome are applied to each one of four error correcting code (ECC) generators 14 along with 64 bits of data. Using a known SECDED algorithm, this is enough syndrome to detect up to two bit errors in the 64 bits of data, and correct one bit error.

By having each DRAM in the example supply one bit of data to each ECC generator, the failure of one DRAM can be tolerated since each ECC generator will detect and be able to correct the resulting bit error. Once error detection and correction is complete each ECC generator 14 strips syndrome from the data and communicates the data to the requestor. During a write operation, the opposite flow of data occurs. A 256 bit block of data is presented by the requester to the memory system and divided between ECC generators 14 into separate 64 bit blocks of data. Each ECC generator computes the required syndrome bit values and adds syndrome data to the 64 bits of data. The resulting 72 bits data block is then stored in memory devices 10.

Error detection and correction by the ECC generators 14 is typically monitored within the computer system. Should any one DRAM fail, the system may "replace" the failed DRAM with a spare (not shown). This replacement process may be performed in background processing while the computer system remains available to users. In the unlikely event of simultaneous failures in two DRAMs, the computer system in the foregoing example could detect the two failures, but remedial action would require maintenance intervention. Such a happenstance would force a system shut-down or switch over to a back-up system. A more powerful error correction algorithm, one capable of correcting two bit errors, would avoid this event.

In sum, conventional memory systems implementing chip-kill read and write both data and syndrome to an ECC generator(s) during each operation. Further, the amount of syndrome furnished by each DRAM to individual ECC generators is dependent on the type of error detection and correction algorithm being used by the computer system. More powerful error detection and correction algorithms require more syndrome bits.

As can be seen from the foregoing example, conventional memory systems use a large number of data lines, or a relatively wide bus. The term "line(s)" is used to describe the physical mechanism by which data bits are electronically communicated from one point to another in a system. A line may take the form, alone or in combination, of a printed circuit board (PCB) strip, metal contact, pin and/or via, microstrip, semiconductor channel, etc. A line may be single or may be associated with a bus. A "bus" is a collection, fixed or variable, of lines, and may also be used to describe the drivers, laches, buffers, and other elements associated with an operative collection of lines. A bus may communicate control information, address information, and/or data. In the foregoing example, four sets of 72 data bit lines connect the memory devices 10 and ECC generators 14. On the other side of the ECC generators, four sets of 64 data bit lines combine to form a 256 bit wide data bus.

Such massively parallel, or wide buses, are required in conventional memory systems due to the slow access speed of memory devices. Wide buses have long been associated with implementation and performance problems, such as excessive power consumption, slow speed, loss of expandability and design flexibility, etc. Thus, various attempts have been made to effectively use relatively narrower buses. In one common approach, packets of data larger than the width of the bus are divided into portions, and the resulting portions are then transmitted over a number of cycles.

Transmission of data over a number of cycles does allow reduction of the bus size. It also greatly increases system complexity. Such complexity often results in memory system rigidity. That is, once implemented in all its complexity, the integration of a new function into the memory system becomes extremely difficult. In particular, memory system designers continue to face enormous challenges in increasing data throughput while minimizing system complexity, and maintaining system reliability.

SUMMARY OF THE INVENTION

The present invention provides a memory system capable of operating in non-chip kill and chip-kill modes. In so doing, the present invention retains the advantages of packetized command and data structures, a simplified bus architecture, high effective data bandwidth, a standard interface, and lower power consumption.

As compared with conventional memory systems, the present invention is able to provide more syndrome bits per data block, thus allowing a broader range of error detection and correction schemes.

The chip-kill mode and/or the non-chip kill mode of operation may be designed and implemented to utilize, for example, cycle multiplexing, bit line multiplexing, or a combination of cycle and bit line multiplexing (i.e., time/space multiplexing).

In one aspect of the present invention, a single memory device responds to a given command, set of commands, instruction, or part of an instruction while the memory system is operating in non-chip-kill mode. However, the same command, set of commands, instruction, or part of an instruction causes a plurality of memory devices to respond while the memory system is operating in chip-kill mode.

In another aspect of the present invention, the packet nature of commands from a memory controller, for example, to a plurality of memory devices is adapted to communicate a command of similar format in either chip-kill or non-chip-kill modes, yet such a similarly formatted command causes one memory device to respond in non-chip-kill mode, while causing a plurality of memory devices to respond in chip-kill mode. This may be done for both read commands and write commands.

BRIEF DESCRIPTION OF THE DRAWINGS

Several embodiments of the present invention are discussed below with reference to the drawings, in which:

FIG. 1 schematically illustrates a conventional memory system implementing chip-kill;

FIG. 2 schematically illustrates a conventional "wide-bus" memory system;

FIG. 3 schematically illustrates an improved memory system comprising a relatively narrow bus;

FIG. 4 schematically illustrates the improved memory system of FIG. 3 in some additional detail;

FIGS. 5A and 5B illustrate exemplary ROW and COL packet command formats, respectively;

FIG. 6 illustrates an exemplary data packet returned in non-chip-kill mode;

FIG. 7 illustrates an exemplary data packet returned in chip-kill mode using cycle (or time) multiplexing;

FIG. 8 illustrates an exemplary data packet returned in chip-kill mode using bit (or bit line space) multiplexing;

FIG. 9 illustrates an exemplary data packet returned in chip-kill mode using time and space multiplexing;

FIG. 10 shows a tabular combination of Col packet device ID and memory device ID inputs addressing a transmission cycle control map;

FIG. 11 is a logic diagram illustrating exemplary transmission cycle mapping hardware;

FIG. 12 shows a logic table for an exemplary exclusive NORing function for the logic comprising the chip-kill decoder of FIG. 11;

FIG. 13 schematically illustrates major elements of an exemplary memory device and memory device interface used in the present invention;

FIG. 14 is a layout diagram illustrating the relationship between several major memory device elements, including the I/O amplifiers shown in FIG. 13;

FIGS. 15 and 16 schematically illustrates the control of the I/O amplifiers of FIGS. 13 and 14 in some additional detail;

FIG. 17 is a diagram illustrating a circuit capable of implementing a delay technique to data bus multiplexing;

FIG. 18 is a flowchart illustrating an exemplary data transfer operation within the context of the present invention;

FIG. 19 is a timing diagram conceptually illustrating the transmission of signals on the channel of the present invention, under a first set of assumed conditions;

FIG. 20 is another timing diagram conceptually illustrating the transmission of signals on the channel of the present invention, under a second set of assumed conditions;

FIG. 21 illustrates the transmission arrangement of a plurality of memory devices performing another, exemplary form of bit multiplexing;

FIG. 22 illustrates one bit line swizzle approach to bit multiplexing; and,

FIG. 23 illustrates another bit line swizzle approach to bit multiplexing.

DETAILED DESCRIPTION

The assignee of the present invention has pioneered the development of next generation memory systems having a relatively narrow, high speed bus(es) and associated memory devices, along with the interface technology required to provide high data throughput. See, U.S. Pat. Nos. 5,319,755; 5,243,703; and 5,254,883, the disclosures of which are incorporated herein by reference.

Very general differences between conventional memory systems and the assignee's memory systems can be seen by comparing FIGS. 2 and 3. In FIG. 2, eight 8-bit memory devices 11 are connected to a memory controller 20 by a 64-bit bus. Assuming 8-bit bytes and a system clock running at 100 MHz, the total data throughput for the conventional system is 800 MB/sec.

In FIG. 3, eight 8-bit memory devices according to the assignees design 13 are connected to a memory controller 22 by two 16 bit data buses. Since each of the assignee's memory devices is capable within the memory system architecture of communicating data on both edges of a 400 MHz clock, for an effective transfer rate of 800 MHz, across a two byte wide channel, the example has a total data throughput of 3.2 GB/sec.

In effect, the assignee's solution replaces costly, conventional memory subsystems and interconnections with a single, standard chip-to-chip bus and improved memory devices. The term "memory device" as used in this document broadly describes a range of devices capable of storing data, and receiving and/or transmitting data at the request of controlling device(s). All forms and configurations of DRAMs, SRAMs, ROM, EPROM, and E.sup.2 PROM devices are contemplated by the term memory device. One defining feature of the term memory device is the presence of electronically accessible data stored in the row and column structure typical in the foregoing devices. Rows within this structure may be further designated into banks and/or pages.

In addition to the referenced U.S. Patents, information describing the assignee's memory systems and memory devices may be had at Rambus.TM. Inc., Mountain View, Calif. See, for example, the Direct RDRAM.TM. 64/72-Mbit Data Sheet, the Direct RAC Data Sheet, the Direct RMC.d1 Data Sheet, A Logical View of the Direct Rambus Architecture, Direct Rambus Technology Overview, Di