An automated method of analyzing crosstalk in a digital logic integrated circuit, the method operating on a digital computer, is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. For at least one potential victim wire of the plurality of wires, determining a subset of the wires of the chip are found to be potential aggressor wires that may couple to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire. The alarm thresholds for each potential victim wire are compared to the calculated height of a coupled noise on the victim wire to determine which, if any, wires of the design suffer enough crosstalk noise that they should be redesigned.

An automated method of analyzing crosstalk in a digital logic integrated circuit on a digital computer is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. The netlist has gate and black box invocations as well as transistor invocations. Library models are used to find driving resistances and capacitances associated with the gate and black-box invocations. For at least one potential victim wire of the plurality of wires, a subset of the wires of the chip are found to be potential aggressor wires to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire. The alarm thresholds for each potential victim wire are compared to the calculated height of a coupled noise on the victim wire to determine which, if any, wires of the design suffer enough crosstalk noise that they should be redesigned.

A system, method, and computer program product for approximating intrinsic capacitance of an integrated circuit (IC) block such as, for example, a compliable memory instance. Estimates of N-well capacitance, metal grid capacitance, and non-switching circuitry capacitance associated with the IC block are obtained. A total intrinsic capacitance of the IC block is then estimated based on the aforesaid constituent estimates.

For analyzing the effects of crosstalk in an electronic device, a model description of the electronic device is provided which defines a victim net and at least one aggressor net, the model description allowing for simulating the dynamic response behaviour at an output of the victim net with respect to an input signal of the victim net and/or of the at least one aggressor net. A characteristic property of the response behaviour at the output of the victim net is represented as an output function of the simulation, the value of the output function depending on input parameters of the simulation. The output function is evaluated as to find an extremum of the output function in a preset range of the input parameters. The characteristic property may in particular be a measure of the delay of the output signal of the victim net with respect to the input signal of the victim net, the input parameters corresponding to the timing of a signal transition applied to the input of the at least one aggressor net with respect to the timing of a signal transition applied to the input of the victim net.

For the purpose of readily specifying a portion of the circuit which has a high possibility of error occurring due to a variation in the supply voltage so that the specified vulnerable portion is countermeasured in a mask layout process, a simulation section simulates the operation of a semiconductor integrated circuit to obtain a transition timing of an input signal that is input to each circuit element. A simultaneous-operation circuit element number detecting section detects, based on a result of the simulation, the number of circuit elements which are supplied with the supply voltage through a common power supply line and in which transition timings of input signals occur within a predetermined time interval (e.g., 0.3 ns or shorter). A supply voltage variation level estimating section estimates the variation level of the supply voltage according to the number of circuit elements which is detected by the simultaneous-operation circuit element number detecting section.