System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module

What is claimed is:

1. A memory test and initialization circuit for testing and initializing a memory and memory interfaces in a data processing system wherein the memory is logically partitioned into a plurality of memory banks, comprising:

(a) a plurality of exerciser testers, one for each of the plurality of memory banks, each of the plurality of exerciser testers comprising:

(i) an address generator to generate a sequence of memory bank addresses to successively address each of the memory banks in a cyclic manner, wherein each of the address generators concurrently addresses a different one of the memory banks;

(ii) a data pattern generator coupled to a corresponding one of the address generators to receive a data pattern control signal upon an output of each of the memory bank addresses generated by its corresponding one of the address generators, and to output a unique data pattern to the memory bank identified by the memory bank address in response to each occurrence of the data pattern control signal; and

(b) a plurality of address initialization registers, one for each of the plurality of exerciser testers, wherein each of the plurality of address initialization registers stores an initial one of the memory bank addresses for one of the memory banks such that each of the address generators is preset to initially address a different one of the memory banks.

2. The memory test and initialization circuit as in claim 1, wherein each memory bank comprises a plurality of data storage locations, and wherein each of the memory bank addresses targeted for a particular one of the memory banks successively addresses each of the data storage locations.

3. The memory test and initialization circuit as in claim 1, wherein the address generators further generate the sequence of memory bank addresses to read the unique data patterns from the plurality of memory banks, and wherein the memory test and initialization circuit further comprises a data compare circuit to receive the unique data patterns read from the plurality of memory banks for comparison to expected data patterns for each of the memory bank addresses.

4. The memory test and initialization circuit as in claim 1, wherein the address generator comprises a counter to generate a data segment count value, wherein each data segment count value corresponds to a different data storage location in the memory banks for storing the unique data patterns.

5. The memory test and initialization circuit as in claim 4, further comprising an address translation circuit coupled to each of the address generators to translate the data segment count value to corresponding ones of the memory bank addresses.

6. The memory test and initialization circuit as in claim 5, further comprising an increment control circuit coupled to the counter to provide an incrementation signal to the counter to control an increment of the data segment count value.

7. The memory test and initialization circuit as in claim 6, wherein the increment control circuit is further coupled to the data pattern generator to generate the data pattern control signals, and wherein the data pattern increments in response to the data pattern control signal such that the data pattern increments upon each output of the memory bank address generated by its corresponding one of the address generators.

8. The memory test and initialization circuit as in claim 6, wherein the increment control circuit generates the incrementation signal in accordance with a predetermined incrementation pattern which causes the memory bank addresses to successively address each of the memory banks in a cyclic manner.

9. The memory test and initialization circuit as in claim 8, wherein the predetermined incrementation pattern comprises incrementing the data segment count value by (N+1) for (N-1) consecutive increments followed by incrementing the data segment count value by 1, and wherein the predetermined incrementation pattern is repeated.

10. The memory test and initialization circuit as in claim 9, further comprising a count terminate register to store a termination count corresponding to a total number of incrementations desired, and wherein the predetermined incrementation pattern is repeated until the termination count is reached.

11. The memory test and initialization circuit as in claim 1, wherein each of the address generation circuits comprises an increment control circuit to provide an incrementation signal to control an increment of the memory bank addresses.

12. The memory test and initialization circuit as in claim 11, further comprising a mode select register to store a mode select value, wherein each of the mode select values select one of a plurality of predetermined incrementation patterns to represent the incrementation signal.

13. The memory test and initialization circuit as in claim 12, wherein a first mode select value causes the memory bank addresses to successively address each of the memory banks in a cyclic manner, and wherein the predetermined incrementation pattern cyclically causes the data segment count value to be incremented by (N+1) for (N-1) consecutive increments followed by incrementing the data segment count value by 1.

14. The memory test and initialization circuit as in claim 12, wherein a second mode select value sets the predetermined incrementation pattern to 1 to cause the memory bank addresses generated by one of the address generators to successively address each of the memory banks in a cyclic manner, and wherein remaining ones of the plurality of exerciser testers are inactive.

15. A method for performing test and initialization of a memory having a plurality of memory banks, comprising:

concurrently generating a plurality of memory bank addresses from a plurality of address generators, wherein each of the concurrently generated memory bank addresses targets a different one of the plurality of memory banks;

providing the memory bank addresses from each particular one of the address generators to each of the plurality of memory banks in a cyclical fashion;

generating an incrementing data pattern for each of the memory bank addresses targeting a particular one of the memory banks, wherein each of the data patterns is written to the memory bank addressed by its corresponding memory bank address;

reading the data patterns from the plurality of memory banks in the same sequence in which the data patterns were written to the plurality of memory banks; and

comparing the data patterns read from the plurality of memory banks to expected data patterns to verify memory and memory interface performance.

16. The method of claim 15, further comprising partitioning the memory into a plurality of logical memory units representing the plurality of memory banks.

17. The method of claim 15, wherein concurrently generating the plurality of memory bank addresses comprises:

generating a plurality of cache line count values; and

translating each of the plurality of cache line count values into the memory bank addresses.

18. The method of claim 17, wherein generating a plurality of cache line count values comprises incrementing a counter in accordance with a predetermined incrementation pattern which causes each of the address generators to successively address each of the memory banks in a cyclical fashion.

19. The method of claim 18, wherein the predetermined incrementation pattern comprises incrementing the data segment count value by (N+1) for (N-1) consecutive increments followed by incrementing the data segment count value by 1, and wherein the predetermined incrementation pattern is repeated.

20. The method of claim 15, further comprising presetting the memory bank addresses from each particular one of the address generators to a predetermined memory bank address prior to generating the memory bank addresses, wherein each of the address generators is preset to initially target a different one of the plurality of memory banks.

21. The method of claim 15, wherein generating an incrementing data pattern for each of the memory bank addresses comprises generating a final data pattern to be provided to each of the memory banks upon completion of the generation of the incrementing data patterns, wherein the final data pattern corresponds to a desired initialized state of the memory banks.

22. A method for performing test and initialization of an SDRAM memory having a plurality of SDRAM memory banks, comprising:

(a) initializing hardware registers to a predetermined logic state;

(b) precharging each of the SDRAM memory banks;

(c) performing a memory refresh operation on each of the SDRAM memory banks;

(d) programming each of the SDRAM memory banks to conform to a desired mode of operation;

(e) performing an exerciser test of each of the SDRAM memory banks, comprising:

(i) concurrently generating a plurality of memory bank addresses from a plurality of address generators, wherein each of the concurrently generated memory bank addresses targets a different one of the plurality of memory banks;

(ii) providing the memory bank addresses from each particular one of the address generators to each of the plurality of memory banks in a cyclical fashion;

(iii) generating an incrementing data pattern for each of the memory bank addresses targeting a particular one of the memory banks, wherein each of the data patterns is written to the memory bank addressed by its corresponding memory bank address;

(iv) reading the data patterns from the plurality of memory banks in the same sequence in which the data patterns were written to the plurality of memory banks; and

(v) comparing the data patterns read from the plurality of memory banks to expected data patterns to verify memory and memory interface performance.

23. A memory test and initialization circuit for testing and initializing a memory and memory interfaces in a data processing system wherein the memory is logically partitioned into a plurality of memory banks, comprising:

(a) a plurality of exerciser test means, one for each of the plurality of memory banks, each of the plurality of exerciser test means comprising:

(i) address generation means for generating a sequence of memory bank addresses to successively address each of the memory banks in a cyclic manner, wherein each of the address generation means concurrently addresses a different one of the memory banks;

(ii) data pattern generation means coupled to a corresponding one of the address generation means for receiving a data pattern control signal upon an output of each of the memory bank addresses generated by its corresponding one of the address generation means, and for outputting a unique data pattern to the memory bank identified by the memory bank address in response to each occurrence of the data pattern control signal; and

(b) address initialization means for storing an initial one of the memory bank addresses for one of the memory banks such that each of the address generation means is preset to initially address a different one of the memory banks.

24. The memory test and initialization circuit as in claim 23, wherein the address generation means comprises cache line count means for generating a cache line count, wherein each cache line count corresponds to a different data storage location in the memory banks for storing the unique data patterns.

25. The memory test and initialization circuit as in claim 24, further comprising address translation means coupled to each of the address generation means for translating the cache line count into corresponding ones of the memory bank addresses.

26. The memory test and initialization circuit as in claim 25, further comprising increment control means coupled to the cache line count means for providing an incrementation signal to the cache line count means to control an increment of the cache line count.

27. The memory test and initialization circuit as in claim 26, wherein the increment control means comprises means for generating the incrementation signal in accordance with a predetermined incrementation pattern which causes the memory bank addresses generated by each of the address generation means to successively address each of the memory banks in a cyclic manner.

Description Submit all comments and votes

FIELD OF THE INVENTION

This invention relates generally to shared memory systems for use in multiprocessing systems, and more particularly to a system and method for initializing and testing all interfaces and memory in a data processing system having multiple memory banks or a memory module partitioned into logical memory units.

BACKGROUND OF THE INVENTION

Large-scale data processing systems typically utilize a tremendous amount of memory. This is particularly true in multiprocessing systems where multiple processing units are implemented. There are several memory methodologies known in the art that provide for efficient use of memory in such multiprocessing environments. One such memory methodology is a distributed memory where each processor has access to its own dedicated memory, and access to another processor's memory involves sending messages via an inter-processor network. While distributed memory structures avoid problems of contention for memory and can be implemented relatively inexpensively, it is usually slower than other memory methodologies, such as shared memory systems.

Shared memory is used in a parallel system, or multiprocessing, system, and can be accessed by more than one processor. The shared memory is connected to the multiple processing units--typically accomplished using a shared bus or network. Large-scale shared memories may be designed to cooperate with local cache memories associated with each processor in the system. Cache consistency, or coherency, protocols ensure that one processor's cached copy of a shared memory location is invalidated when another processor writes to that location.

In order to effectively and efficiently utilize shared memory systems, it may be desirable to configure the shared memory in a predetermined manner prior to use. For example, many shared memory systems employ memory partitioning for executing certain tasks. Generally, a memory partition is a contiguous area of memory within which tasks are loaded and executed, and memory partitioning is the act of designating such memory partitions. A partition includes predetermined characteristics such as a name, a defined size, and a starting address. Where shared memory systems associated with multiprocessing systems are very large, a great deal of overhead may be associated with such memory partitioning. It would therefore be desirable to provide for partitioning the shared memory in the most efficient and timely manner possible.

The data storage in such memory systems should also be capable of initialization to a predetermined state when desired, such as upon initial power application. Other memory locations may also require initialization, such as a directory storage area. Directory storage is used in directory-based cache coherency systems to store cache line state information. A cache line is a predetermined-size data packet that is transferred between the cache memory and the main, shared memory. Extremely large memories can include a correspondingly large volume of cache line storage, which must be tracked by the directory storage. Again, a great deal of time may be consumed during the initialization stage in a computing environment, and it would be desirable to provide a manner of efficiently initializing the shared memory system.

In order to ensure proper operation of the multiprocessing system, testing of the memory to locate and identify faulty memory locations is critical. A faulty storage location can have devastating effects on the operation of the system, particularly where data, executable programs, cache directory structures and the like, are all ultimately reliant on properly functioning memory. However, as is true for initialization functions, pre-processing functions such as memory testing for large-scale memory systems creates additional overhead, causing undesirable start-up delays.

The aggregate effect of performing various types of partitioning, initializing and testing in computer systems having tremendous storage capability is an undesirably lengthy initialization phase. Further, prior art systems typically perform a fixed initialization or testing function without affording flexibility to perform more specific or ad hoc test functions that were not thought of at the time at which fixed test functions were originally established.

It would therefore be desirable to provide an efficient system and method for initializing and testing extensive memory systems, in order to reduce pre-processing operation delays. The present invention provides a high performance mechanism and method for cooperatively testing and initializing a shared memory system having multiple memory banks, and provides flexibility to later afford an opportunity to include newly-created test functions. The present invention therefore provides a solution to shortcomings of the prior art, and offers numerous other advantages over the prior art.

SUMMARY OF THE INVENTION

The present invention provides a system and method for testing and initializing a memory including multiple memory banks or a memory module partitioned into logical memory units. Testing in accordance with the present invention provides for parallel test activities for testing data storage, directory storage, and address and data interfaces.

In accordance with another embodiment of the invention, a memory test and initialization circuit for testing and initializing the memory and memory interfaces in a data processing system is provided. The memory is physically divided into separate memory banks, or alternatively is divided into a plurality of logical memory units. The circuit includes a plurality of exerciser testers, one for each of the plurality of memory banks. Each of the exerciser testers includes an address generator to generate a sequence of memory bank addresses to successively address each of the memory banks in a cyclic manner. Therefore, each address generator addresses a first memory bank, followed by a second memory bank and so forth until each memory bank has been addressed, at which time the address generator again addresses the first memory bank. Each of the address generators in the test and initialization circuit performs this type of cyclic memory bank addressing, however each of the address generators concurrently addresses a different one of the memory banks. A data pattern generator is coupled to a corresponding one of the address generators to receive a data pattern control signal upon each output of each of the memory bank addresses generated by its corresponding address generator. The data pattern generator outputs a unique data pattern to the memory bank identified by the memory bank address in response to each occurrence of the data pattern control signal. In one embodiment, the data pattern generated is an incrementing data pattern, where the increment occurs each time the memory bank address changes. The circuit also includes a plurality of address initialization registers, one for each of the plurality of exerciser testers. Each of the address initialization registers stores an initial memory bank address for one of the memory banks. In this manner, each of the address generators is preset to initially address a different one of the memory banks, and each address generator addresses each memory bank in a cyclical fashion. Therefore, each memory bank is addressed by a different one of the address generators at any given time, which provides for concurrent testing of all memory banks and memory interfaces.

In accordance with another embodiment of the invention, a method for performing test and initialization of a memory having a plurality of memory banks is provided. The method includes concurrently generating a plurality of memory bank addresses from a plurality of address generators, wherein each of the concurrently generated memory bank addresses targets a different one of the plurality of memory banks. The memory bank addresses are provided from each of the address generators to each of the plurality of memory banks in a cyclical fashion. An incrementing data pattern is generated for each of the memory bank addresses targeting a particular one of the memory banks, wherein each of the data patterns is written to the memory bank addressed by its corresponding memory bank address. The data patterns are subsequently read back from the plurality of memory banks in the same sequence in which the data patterns were written to the plurality of memory banks. The data patterns read back from the memory banks are then compared to expected data patterns to verify memory and memory interface performance. In more specific embodiments of the invention, the initialization process includes additional initialization steps for initializing SDRAM memory, including initializing hardware registers to a predetermined logic state, precharging each of the SDRAM memory banks, performing a memory refresh operation on each of the SDRAM memory banks, and programming each of the SDRAM memory banks to conform to a desired mode of operation.

Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. As will be realized, the invention is capable of other and different embodiments, and its details are capable of modification without departing from the scope and spirit of the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described in connection with the embodiments illustrated in the following diagrams.

FIG. 1 is block diagram of a multiprocessor system having multiple memory banks in which the principles of the present invention may be employed;

FIG. 2 is a block diagram of a Symmetrical Multi-Processor (SMP) System Platform in which the principles of the present invention may be applied;

FIG. 3 is a block diagram of one embodiment of a processing module (POD) of a representative SMP;

FIG. 4 is a block diagram of one example of a Sub-Processing Module (Sub-POD) of the representative SMP;

FIG. 5 is a block diagram of a Memory Storage Unit (MSU) of the representative SMP;

FIG. 6 is a block diagram of a Memory Cluster (MCL) of the representative SMP;

FIG. 7 is a block diagram of a Data Crossbar (MDA) in the representative SMP;

FIG. 8 is a block diagram of a Memory Controller (MCA) in the representative SMP;

FIG. 9 is a flow diagram of one embodiment of a multiprocessing system initialization sequence that implements SDRAM memory devices in accordance with the present invention;

FIG. 10 which illustrates one embodiment of a data processing system incorporating the present invention;

FIG. 11 illustrates one embodiment of an Exerciser Tester in accordance with the present invention;

FIG. 12 illustrates the variable incrementation function of an Increment Control module used to assist in the generation of cache line addresses in accordance with the present invention;

FIG. 13 illustrates the cache line address pattern generated by the Increment Control and Counter in each of the Exerciser Testers; and

FIG. 14 illustrates the cache line address pattern as viewed by the Address Buses.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The present invention provides a system and method for testing and initializing a data processing system having multiple memory banks or a memory module partitioned into logical memory units. Testing in accordance with the present invention allows parallel test activities which test data storage, directory storage, and address and data interfaces. A unique addressing scheme is employed to provide address interleaving to test each memory interface. Multiple modes of testing are available to provide testing flexibility, and to account for potential system errors affecting even the initialization procedure.

FIG. 1 is block diagram of a multiprocessor system having multiple memory banks in which the principles of the present invention may be employed. In this embodiment, a plurality of data transfer requesters, labeled Data Requester A 10, Data Requester B 12, Data Requester C 14 through Data Requester n 16 represent entities capable of initiating data transfer requests. These data transfer requests, such as data fetch and data store requests, initiate data transfers between the Data Requesters and the Memory 18. The Memory 18 may be divided into multiple memory banks, such as Memory Bank A 20, Memory Bank B 22, Memory Bank C 24 through Memory Bank n 26. An Address Interface 28 provides the addresses designated by the data transfer request between the appropriate Memory Bank and Data Requester. The Data Interface 30 distributes the data identified for transfer by the data transfer request between the Memory Bank and the Data Requesters.

The system of FIG. 1 includes a plurality of Request Interfaces and Memory Interfaces for both the Address Interface 28 and the Data Interface 30. Each Data Requester is coupled to a Request Interface in the Address and Data Interfaces 28, 30. For example, Data Requester A 10 is coupled to Request Interface A 32 of the Address Interface 28, and to the Request Interface A 34 of the Data Interface 30. Each Data Requester is similarly coupled to corresponding Request Interfaces. A plurality of Memory Interfaces are also provided for both the Address Interface 28 and the Data Interface 30. Each Memory Bank is coupled to a Memory Interface in the Address and Data Interfaces 28, 30. For example, Memory Bank A 20 is coupled to Memory Interface A 36 of the Address Interface 28, and to the Memory Interface A 38 of the Data Interface 30. Each Memory Bank is similarly coupled to corresponding Memory Interfaces.

Addresses are transferred from Request Interfaces in the Address Interface 28 to targeted Memory Banks via corresponding Memory Interfaces, as illustrated by Interface Paths 40. Data is transferred from Request Interfaces in the Data Interface 30 to the addressed Memory Banks via corresponding Memory Interfaces, as illustrated by Interface Paths 42. This data processing arrangement allows for multiple data transfers to occur concurrently.

Testing and initialization of such a system can be complex, and can prove to be quite time-consuming. Where the Memory 18 is very large, writing and verifying test patterns can require an undesirable amount of time. Further, in such a system where a large number of internal interfaces (e.g., Interface Paths 40, 42) are utilized under normal operating conditions, they should be thoroughly tested to ensure proper operation. The Test & Initialization Module 44 performs such testing and initialization.

In order to fully understand the present invention, an example data processing system in which the present invention may be implemented is described below. It is within this context that the present invention is described. Therefore, while the present invention is particularly advantageous in the context of a Symmetrical Multi-Processor (SMP) environment as described below, it will be appreciated by those skilled in the art that the invention is equally applicable to other computing environments requiring management of memory, I/O, or other transaction processing requests. Therefore, the SMP environment described in FIGS. 2-8 is provided for illustrative purposes and to provide a full operational understanding of the invention; however the invention is not limited thereto.

FIG. 2 is a block diagram of a Symmetrical Multi-Processor (SMP) System Platform in which the principles of the present invention may be applied. System Platform 100 includes one or more Memory Storage Units (MSUs) in dashed block 110 individually shown as MSU 110A, MSU 110B, MSU 110C and MSU 110D, and one or more Processing Modules (PODs) in dashed block 120 individually shown as POD 120A, POD 120B, POD 120C, and POD 120D. Each unit in MSU 110 is interfaced to all PODs 120A, 120B, 120C, and 120D via a dedicated, point-to-point connection referred to as an MSU Interface (MI) in dashed block 130, individually shown as 130A through 130S. For example, MI 130A interfaces POD 120A to MSU 110A, MI 130B interfaces POD 120A to MSU 110B, MI 130C interfaces POD 120A to MSU 110C, MI 130D interfaces POD 120A to MSU 110D, and so on.

In this example SMP environment, MI 130 comprises separate bi-directional data and bi-directional address/command interconnections, and further includes unidirectional control lines that control the operation on the data and address/command interconnections (not individually shown). The control lines operate at a system clock frequency (SYSCLK) while the data bus runs source synchronous at two times the system clock frequency (2.times.SYSCLK). For example, in one embodiment, the system clock frequency is approximately 100 megahertz (MHZ).

Any POD 120 has direct access to data in any MSU 110 via one of MIs 130. For example, MI 130A allows POD 120A direct access to MSU 110A and MI 130F allows POD 120B direct access to MSU 110B. PODs 120 and MSUs 110 are discussed in further detail below.

System Platform 100 further comprises Input/Output (I/O) Modules in dashed block 140 individually shown as I/O Modules 140A through 140H, which provide the interface between various Input/Output devices and one of the PODs 120. Each I/O Module 140 is connected to one of the PODs across a dedicated point-to-point connection called the MIO Interface in dashed block 150 individually shown as 150A through 150H. For example, I/O Module 140A is connected to POD 120A via a dedicated point-to-point MIO Interface 150A. The MIO Interfaces 150 are similar to the MI Interfaces 130, but may have a transfer rate that is approximately half the transfer rate of the MI Interfaces because the I/O Modules 140 are located at a greater distance from the PODs 120 than are the MSUs 110.

FIG. 3 is a block diagram of one embodiment of a processing module (POD). POD 120A is shown, but each of the PODs 120A through 120D have a similar configuration. POD 120A includes two Sub-Processing Modules (Sub-PODs) 210A and 210B. Each of the Sub-PODs 210A and 210B are interconnected to a Crossbar Module (TCM) 220 through dedicated point-to-point Interfaces 230A and 230B, respectively, that are similar to the MI interconnections 130. TCM 220 further interconnects to one or more I/O Modules 140 via the respective point-to-point MIO Interfaces 150. TCM 220 both buffers data and functions as a switch between Interfaces 230A, 230B, 150A, and 150B, and MI Interfaces 130A through 130D. When an I/O Module 140 or a Sub-POD 210 is interconnected to one of the MSUs via the TCM 220, the MSU connection is determined by the address provided by the I/O Module or the Sub-POD, respectively. In general, the TCM maps one-fourth of the memory address space to each of the MSUs 110A-110D. The TCM 220 can further be configured to perform address interleaving functions to the various MSUs. The TCM may also be utilized to perform address translation functions that are necessary for ensuring that each processor (not shown in FIG. 3) within each of the Sub-PODs 210 and each I/O Module 140 views memory as existing within a contiguous address space as is required by certain off-the-shelf operating systems.

FIG. 4 is a block diagram of one example of a Sub-Processing Module (Sub-POD) 210A. Sub-POD 210A i