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Claims  |
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What is claimed is:
1. An electronic circuit comprising:
a first test access port including a predetermined set of input and output lines including a test data input line, said first test access port adapted for controlling electronic test of the electronic circuit and operating in accordance with a
predetermined set of a plurality of test states, said predetermined set of test states including a data input state and an instruction input state;
a plurality of testable embedded core circuits each having a second test access port including said predetermined set of input and output lines adapted for controlling electronic test of said testable embedded core circuit, each second test
access port operating in accordance with said predetermined set of a plurality of test states;
a test access port controller connected to said first test access port, said test access port controller including a switch data register loadable from said test data input line when said first test access port is in said at least one data input
state;
a programmable switch coupled to said first test access port and said second test access port of each of said plurality of testable embedded core circuits, said programmable switch selectively connecting said first test access port to either no
second test access port of any testable embedded core circuit or to said second test access port of a selected one of said at least one testable embedded core circuit for controlling test of said embedded core circuit dependent upon data stored in said
switch data register; and
said test access port controller responsive to said test data input line when said programmable switch connects said first test access port to said second test access port of one of said plurality of testable embedded core circuits, said test
access port controller operating in a one of a plurality of snoopy states corresponding to said test state of said second test access port, said test access port including a snoopy instruction register loadable from said test data input line when said
test access port controller is in a snoopy state corresponding to an instruction input state of one of said plurality of testable embedded core circuits, said test access port controller controlling said programmable switch to disconnect said first test
access port from said second test access port of all said at least one testable embedded core circuit when said snoopy instruction register stores a predetermined wake-up instruction.
2. The electronic circuit of claim 1, wherein:
said second test access port of each testable embedded core circuit includes an instruction register loadable from said test data input during said instruction input state;
said predetermined set of test states includes an update instruction register state for confirming update of data loaded into an instruction register;
said test access port controller controls said programmable switch to disconnect said first test access port from said second test access port of all said plurality of testable embedded core circuits when said snoopy instruction register stores
said predetermined wake-up instruction in a snoopy state corresponding to said update instruction register state.
3. The electronic circuit of claim 1, wherein:
said second test access port of each of said plurality of testable embedded core circuits includes an instruction register loadable from said test data input during said instruction input state;
said snoopy instruction register of said test port controller includes more bits than said instruction register of said second test access port each of said plurality of testable embedded core circuits.
4. The electronic circuit of claim 3, wherein:
said predetermined set of test states includes an update instruction register state for confirming update of data loaded into an instruction register;
said test access port controller controls said programmable switch to disconnect said first test access port from said second test access port of all said plurality of testable embedded core circuits when said snoopy instruction register stores
said predetermined wake-up instruction in a snoopy state corresponding to said update instruction register state.
5. The electronic circuit of claim 3, wherein:
said predetermined set of test states includes an update instruction register state for confirming update of data loaded into an instruction register;
said test access port controller further includes a counter for counting instruction bits received on said test data input line during a snoopy state corresponding to said instruction register input state; and
said test access port controller controls said programmable switch to disconnect said first test access port from said second test access port of all said plurality of testable embedded core circuits when a count in said counter exceeds a
predetermined value in a snoopy state corresponding to said update instruction register state.
6. The electronic circuit of claim 5, wherein:
said test port access controller further includes a data register loadable in said data input state; and
said predetermined value is a value corresponding to a predetermined set of bits of said data register.
7. The electronic circuit of claim 1, further comprising:
at least one non-testable embedded core circuit not having a test port for controlling electronic test of said non-testable embedded core circuit; and
wherein said test access port controller is further connected to said at least one non-testable embedded core circuit and is further adapted for controlling test of said at least one non-testable embedded core circuit.
8. The electronic circuit of claim 1, wherein:
said electronic circuit including said first test access port, said at least one testable embedded core circuit, said test access port controller and said programmable switch is disposed upon a single integrated circuit.
9. A method of testing an integrated circuit comprising the steps of:
providing a first test access port having a predetermined set of input and output lines including a test data input line, said first test access port adapted for controlling electronic test of the electronic circuit and operating in accordance
with a predetermined set of a plurality of test states, said predetermined set of test states including a data input state and an instruction input state;
embodying in the integrated circuit a plurality of testable embedded core circuits each having a second test access port including said predetermined set of input and output lines adapted for controlling electronic test of said testable embedded
core circuit, each second test access port operating in accordance with said predetermined set of a plurality of test states;
embodying in the integrated circuit a test access port controller connected to said first test access port, said test access port controller including a switch data register loadable from said test data input line when said first test access port
is in said at least one data input state;
embodying in the integrated circuit a programmable switch coupled to said first test access port and said second test access port of each of said at least one testable embedded core circuit, said programmable switch selectively connecting said
first test access port to either said second test access port of no testable embedded core circuit or to said second test access port of a selected one of said plurality of testable embedded core circuits for controlling test of said embedded core
circuit dependent upon data stored in said switch data register; and
said test access port controller responsive to said test data input line when said programmable switch connects said first test access port to said second test access port of one of said plurality of testable embedded core circuits, said test
access port controller operating in a one of a plurality of snoopy states corresponding to said test state of said second test access port, said test access port including a snoopy instruction register loadable from said test data input line when said
test access port controller is in a snoopy state corresponding to an instruction input state of one of said testable embedded core circuits, said test access port controller controlling said programmable switch to disconnect said first test access port
from said second test access port of all said plurality of testable embedded core circuits when said snoopy instruction register stores a predetermined wake-up instruction.
10. The method of claim 9, further comprising the steps of:
loading an instruction register of said second test access port of said one of said plurality of testable embedded core circuit connected to said first test access port from said test data input during said instruction input state;
wherein said predetermined set of test states includes an update instruction register state for confirming update of data loaded into an instruction register; and
controlling said programmable switch to disconnect said first test access port from said second test access port of all said plurality of testable embedded core circuits when said snoopy instruction register stores said predetermined instruction
in a snoopy state corresponding to said update instruction register state.
11. The method of claim 9, further comprising the steps of:
loading an instruction register of said second test access port of said one of said plurality of testable embedded core circuit connected to said first test access port from said test data input during said instruction input state; and
wherein said snoopy instruction register of said test port controller includes more bits than said instruction register of said second test access port each of said plurality of testable embedded core circuits.
12. The method of claim 11, wherein:
said predetermined set of test states includes an update instruction register state for confirming update of data loaded into an instruction register; and
said method further includes the step of controlling said programmable switch to disconnect said first test access port from said second test access port of all said plurality of testable embedded core circuits when said snoopy instruction
register stores said predetermined wake-up instruction in a snoopy state corresponding to said update instruction register state.
13. The method of claim 12, wherein:
said predetermined set of test states includes an update instruction register state for confirming update of data loaded into an instruction register;
said test access port controller further includes a counter for counting instruction bits received on said test data input line during said snoopy instruction register input state; and
said method further includes the step of controlling said programmable switch to disconnect said first test access port from said second test access port of all said plurality testable embedded core circuits when a count in said counter exceeds a
predetermined value in a snoopy state corresponding to said update instruction register state.
14. The method of claim 13, further comprising the step of:
loading a data register of said test port access controller in said data input state; and
wherein said predetermined value is a value corresponding to a predetermined set of bits of said data register.
15. The method of claim 9, further comprising the steps of:
embodying in said integrated circuit at least one non-testable embedded core circuit not having a test port for controlling electronic test of said non-testable embedded core circuit; and
controlling test of said at least one non-testable embedded core circuit via said test access port controller.
16. The method of claim 9, further comprising the steps of:
testing said integrated circuit by sequentially for each testable embedded core circuit
controlling said programmable switch to connect said second test access port of one of said plurality of testable embedded core circuits to said first test access port,
supplying said corresponding test vector to said first test access port,
supplying data on said test data input line of said first test access port to load said predetermined wake-up instruction into said snoopy instruction register when in a snoopy state corresponding to said instruction input state,
controlling said programmable switch to disconnect said second test port of all of said plurality of testable embedded core circuits from said first test access port, and
supplying data on said test data input line of said first test access port to change said internal state of said test access port controller to load said switch data register with data to control said programmable switch to connect said second
test access port of a next one of said plurality of testable embedded core circuits until all testable embedded core circuits are tested. |
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Description |
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TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is test access ports for integrated circuits and more particularly a manner to integrate core logic modules each having a test access port.
BACKGROUND OF THE INVENTION
Continuous decrease in feature size of transistors has led to the recent trend of core-based design. Today's integrated circuit (IC) becomes tomorrow's integratable core. Today's printed circuit board becomes tomorrow's IC. This decrease in
feature size leads to the availability of unprecedented number of transistors on an integrated circuit. Current technology trends lead to projections of further rise in the number of transistors that may be integrated into a single IC. This expected
trend in IC technology is leading to a re-prioritization of design issues. The traditional concern of gate/transistor count is becoming relatively less important. Issues like re-usability of existing designs, and minimization of design cycle time, are
increasing continuously in importance. A major design problem for large integrated circuits is testability. Moreover, both the recurring and non-recurring test costs of such complex products now constitute a significant fraction of the total cost of
the product. It is now likely that a single large IC will employ one or more preexisting cores. Currently the most widely accepted test standard for integrated circuits is IEEE Standard 1149.1, also known as JTAG. This standard was created with the
primary goal of alleviating board-test problem via Test Access Ports (TAPs). The JTAG standard cannot be directly used in IC's containing cores which already include Test Access Ports. At the same time, widespread acceptance of JTAG in the electronics
and semiconductor industry requires current and future IC's to be fully compliant with this standard. Thus there is a great need to develop a test access mechanism that allows embedded cores and non-core logic in an IC to be accessed via a well-defined
JTAG interface.
Recently, some solutions have been proposed to address this problem that either violate the JTAG standard, or require modification of the TAP in existing cores, or follow a completely different Built-In Self Test (BIST) based technique to testing
embedded cores, without addressing the issue of JTAG compliant test access to the embedded cores.
SUMMARY OF THE INVENTION
This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a first test access port, preferrably compliant with the IEEE Standard 1149.1 commonly known as JTAG. The electronic
circuit includes at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. The test access port controller is
preferrably also JTAG compliant. An internal state in the test access port controller, such as bits in a data register, controls the switch state of the programmable switch. The programmable switch is controlled to selectively connect the first test
access port to the embedded core circuits. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the
embedded core circuit under test. The test access port controller can control the programmable switch to regain control of the first test access port and disconnect all of the embedded core circuits when in snoopy states. This may occur upon detection
of a wake-up instruction loaded into a snoopy instruction register during a snoopy state corresponding to an instruction input state. Alternatively, a count of instruction bits more than the most bits for instruction input for any embedded core can
trigger the wake-up function.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other aspects of this invention are illustrated in the drawings, in which:
FIG. 1 illustrates the features of the prior art JTAG test access port as connected to a circuit under test;
FIG. 2 illustrates the state diagram of the prior art JTAG test access port;
FIG. 3 illustrates a first prior art technique to include plural cores with JTAG compliant test access ports in a single integrated circuit in which the plural test access ports are serially connected;
FIG. 4 illustrates a second prior art technique to include plural cores with JTAG compliant test access ports in a single integrated circuit in which the plural test access ports are selectively connected;
FIG. 5 illustrates a third prior art technique to include plural cores with JTAG compliant test access ports in a single integrated circuit known as test access port linking architecture;
FIG. 6 illustrates the state diagram of the prior art test access port linking architecture;
FIG. 7 illustrates the inventive technique for including plural cores with JTAG compliant test access ports in a single integrated circuit;
FIG. 8 illustrates the features of the programmable switch of this invention illustrated in FIG. 7;
FIG. 9 illustrates one manner in which the switch data register controls the state of the programmable switch;
FIG. 10 illustrates an alternative manner in which the switch data register controls the state of the programmable switch;
FIG. 11 illustrates the features of the snoopy test access port of this invention illustrated in FIG. 7;
FIG. 12 illustrates the state diagram of the snoopy test access port of this invention;
FIG. 13 illustrates an expanded view of two of the states of the snoopy test access port illustrated in FIG. 11;
FIG. 14 illustrates a use of the hierarchical test access port of this invention;
FIG. 15 illustrates the construction of snoopy test access port employing an alternative manner of returning from snoopy state;
FIG. 16 illustrates a state diagram of the alternative of FIG. 15;
FIG. 17 illustrates the construction of snoopy test access port employing a second alternative manner of returning from snoopy state; and
FIG. 18 illustrates a state diagram of the second alternative of FIG. 17.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
FIG. 1 illustrates the basic parts of a JTAG interface, which specifies a test architecture for exemplary integrated circuit 100. Integrated circuit 100 includes core logic 110 and various normal input/output pins 111 and 113. This standard
permits internal scan, boundary scan, built-in self-test (BIST), and vendor-specific design-for-testability features all to be accessed and controlled via the same test access port (TAP). The overall structure of the TAP includes four essential parts: a
TAP controller 121; an instruction register (IR) 123, which can be loaded with instructions related to various test actions; a decode logic 125 which decodes the contents of instruction register 123 to generate appropriate control signals; and a set of
other registers called data registers. The data registers must include a boundary scan register (BSR). In FIG. 1 boundary scan register 127 is illustrated as parts 127a to 127h, which connect to respective input/output lines 111 and 113. FIG. 1
further illustrates two data registers bypass register 129 and ID register 131. The JTAG standard permits circuit specific data registers which commonly include various registers in the circuit under test (CUT).
The TAP controller 121 is a 1-input synchronous sequential circuit whose operation is controlled via two pins. These two pins are: test mode select TMS 133; and test clock TCK 135. The test mode select pin 133 serves as the sole input to TAP
controller 121. The TAP specification requires two other pins: test data input TDI 137; and test data output TDO 139. The test data input pin 137 and the test data output pin 139 are used to serially shift into and out of various registers including
circuit specific registers. The TAP specification permits an optional test reset pin TRST* 141. The test reset pin 141 facilitates resetting of the TAP controller 121. In general, data is loaded into the various data registers via test data input pin
137 and instructions are loaded into instruction register 123 also via test data input pin 137. These instructions are decoded via decoder logic 125 to enable various actions like a scan test, BIST, emulation, etc. Results of the tests may be read out
of the data registers via test data output pin 139.
FIG. 2 illustrates a state diagram of test access port controller 121 as specified in the JTAG standard. All the signals illustrated are input at the test mode select pin 133 which are read at edges of the test clock. Test access port
controller 121 is initially in test logic reset state 201. Test access controller 121 remains in Test Logic Reset state 201 while test mode select TMS is 1. If test mode select TMS becomes 0, then test access controller 121 transits to the Run
Test/Idle state 202. Test access port controller 121 remains in the Run Test/Idle state while test mode select remains 0. If test mode select TMS becomes 1, then test access port controller 121 transits to Select Data Register-Scan state 210. Data
from test data input TDI can be scanned into a selected data register in the Shift-Data Register state 211 or the process caused in Pause-Data Register state 214. From either Exit 1-Data Register state 213 or Exit 2-Data Register state 215, Update-Data
Register state 216 updates the selected data register. If test mode select TMS is 0, then test access controller 121 returns to Run Test/Idle state 202. If test mode select TMS is 1, then test access controller 121 returns to Select Data Register-Scan
state 210 to access another data register. According the JTAG standard the number of data registers and their length is implementation dependent. A similar loop including states 220 to 226 permits selection and scan into an instruction register. The
JTAG standard specifies a single instruction register whose length is implementation dependent. The details of this state diagram are not important to this invention. It is sufficient to note that for any particular implementation of a test access port
controller, it is possible to place the JTAG interface into a mode to shift in data from test data input pin 137 into any of the data registers and into the instruction register.
The JTAG standard was formulated with the goal of allowing exactly one test access port per IC. This standard does not take into account the possibility of designs containing multiple cores, some of which already have JTAG compliant test access
ports. Consequently, the rapid rise in designs using multiple cores from a variety of vendors has made this shortcoming of JTAG, a major problem. Quite often, the JTAG compliant test access port in a core is inherited from its past as a standalone IC.
This JTAG compliant test access port is intimately tied to testing and/or emulation strategies of the core. In many instances these cannot be easily changed. In many instances the semiconductor manufacturer has no access to the actual design which was
purchased as a package from a core intellectual property vendor. Thus changes related to the test access port are impossible. Even if the manufacturer has access to the design, a new test access port design incurs extremely high expenses of reworking
the tests and/or the emulation methodology. As a result, various ad-hoc solutions have emerged. There may be two or more such cores in a single integrated circuit. In addition, a typical integrated circuit having a core based design includes
additional circuits not having an included test access port. The final integrated circuit design preferably includes a JTAG compliant test access port for testing these non-TAPed cores (NTC).
FIG. 3 illustrates an example of a first known strategy dealing with this problem. In FIG. 3 the plural test access ports are serially connected. Integrated circuit 300 includes a boundary scan register (ICBSR) 305 similar to boundary scan
register 127 illustrated in FIG. 1. Integrated circuit 300 includes plural non-TAPed cores referred to generally as 310 and TAPed cores 320 and 330. The non-TAPed cores 310 are connected to a first test access port TAP1317. Test access port 317 is
provided in the same manner as for original JTAG compliant designs. First TAPed core 320 includes its own core boundary scan register CBSR and a second test access port 327. Similarly, second TAPed core 330 includes core boundary scan register (CBSR)
335 and a third test access port TAP3337. Each of the TAPed cores 320 and 330 forms a JTAG compliant system with its respective test access port TAP2327 and TAP3337. Both core boundary scan registers 325 and 335 are coupled to integrated circuit
boundary scan register 305. A single scan chain from test data input TDI to test data output TDO is created for all test access ports in the entire integrated circuit 300. Though FIG. 3 illustrates three test access ports TAP1317, TAP2327 and TAP3337,
one skilled in the art would realize this technique could be used for integrated circuits with as few as two test access ports and for greater numbers of test access ports. The test data input TDI for integrated circuit 300 is coupled to the test data
input of test access port 317. The test data output of test access port 317 is connected to the test data input of test access port 327. The test data output of test access port 327 is connected to the test data input of test access port 337. Finally,
the test data output of test access port 337 forms the test data output TDO for integrated circuit. 300. The effectively chains up the test access ports in the embedded cores with the test access port providing test access to the entire integrated
circuit 300. The other JTAG lines test clock TCK, test mode select TMS and test reset TRST* (if present) are connected to all the test access ports 317, 327 and 337 in parallel. This maintains the same integrated circuit pins as required of a single
test access port.
The major problem with this approach is that the resultant design is essentially non-compliant with JTAG. Multiple test access port controllers get exercised in every clock cycle. Theoretically, one could compose test access port TAP1317, test
access port TAP2327 and test access port TAP3337 to create a composite TAP to force compliance with the JTAG framework. In reality, this is not an option. Core vendors are unlikely to provide all the information necessary to model the composite TAP.
More importantly, the cost of creating such a model will be unacceptably high.
FIG. 4 illustrates a second known technique for combining plural cores with independent JTAG compliant test access ports on a single integrated circuit. In FIG. 4 the plural test access ports are individually selectable. Integrated circuit 400
includes a boundary scan register (ICBSR) 405, plural non-TAPed cores referred to generally as 410 serviced by test access port 417 and TAPed cores 420 and 430 in a manner similar to integrated circuit 300 illustrated in FIG. 3. In integrated circuit
400 all the pins specified in the JTAG standard, including test data in TDI, test data out TDO, test clock TCK, test mode select TMS and test reset TRST* (if present), are connected in parallel to all the test access ports 417, 427 and 437. This
technique relies on the tri-state output requirement on the test data output TDO pins when the test access port is idle to be able to tie these together into one net. This technique uses extra select pins S0 and S1 to selectively enable individual test
access ports 417, 427 and 437. This is needed in order to allow proper functioning of the test access ports when driven in parallel.
This second technique poses problems. The JTAG standard does not have any provision for the select pins S0 and S1. Consequently, extra logic needs to be added to each test access port to allow such selection via these selection pint. More
importantly, the number of select pins increases with the number of embedded cores. This is likely to constitute an unacceptably high pin overhead, as the number of embedded cores in a single integrated circuit continues to increase. These select pins
are also not recognized by the existing software tools for modeling and simulation of test access ports. Finally, the extra pins lead to extra routing in the system board. Overall, it is thus felt that the use of select pins to selectively enable TAPs,
is not an acceptable solution.
FIG. 5 illustrates a third known technique for combining plural cores with independent JTAG compliant test access ports on a single integrated circuit. Integrated circuit 500 includes a boundary scan register (ICBSR) 505, plural non-TAPed cores
referred to generally as 510 serviced by test access port 517 and TAPed cores 520 and 530 in a manner similar to integrated circuit 300 illustrated in FIG. 3 and integrated circuit 400 illustrated in FIG. 4. Lee Whetsel proposed this systematic solution
to this problem, which is designated the test access port linking architecture (TLA), in Whetsel, L., "An IEEE 1149.1 Based Test Access Architecture for INTEGRATED CIRCUITS with Embedded Cores," Proc. Int'l. Test Conference, 1997. In this approach,
the test bus according to the JTAG specified inputs and outputs is connected to a special module designated the test access port linking module TLM 540. The test access port linking module 540 is a finite-state machine which controls access to the test
bus and selectively enables/disables the various test access ports 517, 527 and 537. The test access ports 517, 527 and 537 are connected to the integrated circuit JTAG inputs and outputs via test access port linking module 540. Test access port
linking module 540 generates enable signals ENA1, ENA2 and ENA3 for corresponding test access ports TAP1517, TAP2527 and TAP3537. Test access port TAP1527 is selected at power-up or when test access port linking module 540 is reset. Test access port
linking module 540 is a shared resource between the test access ports TAP1517, TAP2527 and TAP3537. The state of test access port linking module 540 can be accessed and changed by the currently enabled test access port. This is achieved via the select
signals SEL1, SEL2 and SEL3.
FIG. 6 illustrates the state diagram of a system employing test access port linking module 540. In order to achieve proper selection and de-selection of the embedded cores using the test access port linking module 540, the state diagrams of the
embedded test access port controllers must be modified. The test access ports leave Run Test/Idle state 602 only when both test mode select TMS and the corresponding enable ENA signal are 1. The update-Data Register state 616 links or unlinks depending
upon the state of both the test mode select TMS signal and the corresponding enable ENA signal. Other portions of the test port controller state diagram are the same as the prior JTAG standard as illustrated in FIG. 2.
The test access port linking architecture (TLA) has several advantages over the other ad-hoc approaches illustrated in FIGS. 3 and 4. The test access port linking architecture forces synchronous transition of all test access ports and the test
access port linking module from initial the reset state to the Run Test/Idle state. This technique allows the initially enabled test access port TAP1 to follow the test bus from Run Test/Idle state, while the non-enabled test access ports remain in the
Run Test/Idle state. The test access port linking module allows all linking/unlinking operations to happen only in the Update-Data Register state. All unlinked test access ports automatically go to the Run Test/Idle state. This ability is especially
useful for allowing cores with non-enabled test access ports to provide inputs to the core with the enabled test access port or allowing cores with non-enabled test access ports to run built-in self test (BIST) while the core with an enabled test access
is exercised via the test bus. The test access port linking module also allows some flexibility in synchronizing the enabled test access ports state to the state of the test bus.
While the test access port linking architecture addresses several problems of other ad-hoc approaches to handling of embedded cores with built-in test access ports, many concerns remain. The fact that the existing test access ports in the
embedded cores need to be modified to add extra ports and logic is a major concern. Extra hardware is needed to generate the SEL signal and extra logic is needed to properly handle the ENA signal. While the actual amount of hardware involved is small,
such changes to the test access port involve significant non-recurring expense (NRE) in terms of validating the changes in the context of a given core. A more significant concern stems from the requirement that the embedded test access port controller
state-diagrams be modified as illustrated in FIG. 6. This involves non-trivial effort re-design of the core and non-trivial changes to the software tools that model and simulate the test access environment. Given the amount of time needed to adopt
accept the JTAG standard, any suggestion of a major re-design of existing parts is likely to meet with resistance from the vendors. Yet another concern arises out of the use of a separate test access port controller in the test access port linking
module on top of test access port TAP1 used to provide JTAG compliant test access to the entire integrated circuit. The amount of logic involved is not large, but it is nevertheless overhead.
The most significant concern about the test access port linking architecture, stems from likely consequences of the rapid increase in the number of devices on an integrated circuit. The test access port linking architecture may not be able to
provide the type of hierarchical test access solution that will be necessary. The following two examples illustrate possible shortcomings of the test access port linking architecture, in the context of future integrated circuit technologies. For
systems where time to market is critical, and cost per piece is of secondary importance, it is widely expected that the board of today will become a single integrated circuit tomorrow, and an integrated circuit of today will become an embedded core
tomorrow. When that happens, the test access port requirements for the core which includes the SEL and ENA ports will be different from the test pin requirements for today's integrated circuit which has no room for SEL and ENA pins in its JTAG compliant
interface. Consequently, the test access port must be re-designed when the integrated circuit design becomes an embedded core. This would involve significant non-recurring expense. Even if today's integrated circuit were to be designed with a test
access port linking module, when that integrated circuit design becomes an embedded core, the test access port linking module will have to be replaced by a test access port linking module that has SEL and ENA ports, since the integrated circuit design
test access port linking module would have no room for the required SEL and ENA ports. Thus the test access port linking architecture does not provide a truly hierarchical solution to the test access problems for systems with multiple-levels of embedded
cores, such as are foreseen in not-too-far future. With the advent of very short-channel integrated circuit technologies allowing billions of transistors to be integrated in one device, designers are likely to embed many tens of cores in one integrated
circuit. Providing proper test access in such a design, will require the creation of a hierarchy of test access port linking modules. Two types of test access port linking modules will be required: the test access port linking module as proposed by
Whetsel at the highest level of hierarchy; and a modified test access port linking module with SEL and ENA ports at lower levels of hierarchy.
FIG. 7 illustrates the hierarchical test access port (HTAP) of this invention for combining plural cores with independent JTAG compliant test access ports on a single integrated circuit. Integrated circuit 700 includes a boundary scan register
(ICBSR) 705, plural non-TAPed cores referred to generally as 710 serviced by test access port 717 and embedded TAPed cores 720 and 730 in a manner similar to integrated circuit 300 illustrated in FIG. 3, integrated circuit 400 illustrated in FIG. 4 and
integrated circuit 500 illustrated in FIG. 5. From a functional point of view, the hierarchical test access port (HTAP) performs three major tasks in order to provide systematic and truly hierarchical test access to embedded cores. Firstly, the
hierarchical test access port 727 preforms normal JTAG compliant test access port operations for the non-TAPed cores 710. Secondly, the hierarchical test access port 717 coordinates connection between the test bus and test access ports in embedded cores
via a programmable switch 740. Lastly, hierarchical test access port 717 monitors the test access port currently being exercised via the test bus when an embedded test access port is in control of the test bus. This monitoring is accomplished via a
snooping mechanism. The hierarchical test access port continues to monitor the test mode select line after yielding the test bus to an embedded test access port. The hierarchical test access port consists of two distinct blocks, a snoopy test access
port (SN-TAP) 717 and a programmable switch 740. The programmable switch 740 is a crossbar switch with a flip-flop at each interconnection point. FIG. 7 illustrates an overall view of an example system employing a hierarchical test access port that
includes two embedded cores and several pieces of non-core logic.
FIG. 7 illustrates the structural features of the hierarchical test access port of this invention. The test clock TCK pin of integrated circuit 700 is connected to the snoopy test access port 717 and to all embedded test access ports 727 and
737. This connection may optionally be made via a not illustrated buffer tree if necessary for drive considerations. The test mode select TMS and test data input TDI pins of integrated circuit 700 are connected directly to snoopy test access port 717
and to programmable switch 740. The test data output TDO output of snoopy test access port 717 is connected only to programmable switch 740. The embedded test access ports 727 and 737 receive their test mode select TMS and test data input TDI inputs
from programmable switch 740. The embedded test access ports 727 and 737 supply their test data outputs TDO only to programmable switch 740. The test data output TDO of integrated circuit 700 is supplied by programmable switch 740. The optional test
reset TRST* pin of integrated circuit 700 is supplied to snoopy test access controller 717 and may be passed on to programmable switch 740.
FIG. 8 illustrates details of programmable switch 740. Control of the state of programmable switch 740 is provided by switch data register SDR 801. Switch data register SDR 801 is a data register controllable by snoopy test access port 717.
Switch 803 is essentially a crossbar switch between test mode select TMS, test data input TDI and test data outputs TDO1, TDO2 and TDO3 as inputs and test mode select TMS2 and TMS3 and test data inputs TDI2 and TDI3 as outputs. Each crosspoint
controlled by a flip-flop (or latch, if appropriate). These flip-flops together constitute switch data register 801. Switch data register 801 is controlled by snoopy test access port 717 and hence can be set to any combination of values shifted in via
the integrated circuit TDI pin. This permits virtually any interconnection between the embedded test access ports. Some of the possible interconnection modes may not be JTAG compliant. Such non-compliant interconnection modes may be used for
vendor-specific testing of integrated circuit 700.
Switch data register SDR 801 is controlled via a set of signals generated by snoopy test access port 717 known collectively as switch control. These signals are an implementation dependent control permitted by the JTAG standard. As seen in FIG.
8, the test data output TDO of snoopy test access port 717 and the serial output of switch data register 801 require somewhat special handling. This will is discussed below.
FIGS. 9 and 10 illustrate alternative manners in which switch data register 801 controls switch 803. Switch 803 is a crossbar with horizontal lines connected to integrated circuit 700 test mode select TMS, test data input TDI and test data
output TDO pins. The vertical lines are connected to the JTAG connections of the various embedded cores. Crosspoint connections 811 optionally connect corresponding horizontal and vertical lines. For example, switch 803 could have crosspoints 811
enabled to connect the integrated circuit 700 test mode select TMS, test data input TDI and test data output | | |
