Semiconductor device with self refresh test mode

What is claimed is:

1. A semiconductor device comprising:

an interface for receiving self refresh test control signals from an external device;

a memory array;

a self refresh test mode controller coupled to the interface for outputting internal test control signals in response to the self refresh test control signals during a self refresh test mode of the semiconductor device;

self refresh circuitry coupled to the self refresh test mode controller for producing refresh signals including preliminary refresh signals and location refresh signals in response to the internal test control signals during the self refresh test mode, with at least some of the preliminary refresh signals being used in producing the location refresh signals; and

selection circuitry coupled to the self refresh circuitry and the memory array for selecting memory locations within the memory array to be refreshed in response to the location refresh signals.

2. The semiconductor device of claim 1, wherein the self refresh test mode controller includes circuitry for outputting indicating signals that are indicative of at least one of the refresh signals through the interface to the external device.

3. The semiconductor device of claim 2, wherein the indicating signals are indicative of the location refresh signals.

4. The semiconductor device of claim 2, wherein the indicating signals are indicative of at least some of the preliminary refresh signals.

5. The semiconductor device of claim 2, wherein the indicating signals are indicative of at least some of the preliminary refresh signals and of the location refresh signals.

6. The semiconductor device of claim 1, wherein the memory array includes rows and columns, and the memory locations selected by the selection circuitry are rows.

7. The semiconductor device of claim 1, wherein the refresh signals include row address strobe signals.

8. The semiconductor device of claim 1, wherein the refresh signals include column address strobe signals.

9. The semiconductor device of claim 1, wherein the memory array is a first memory array, and further comprising a second memory array that is refreshed in response to the self refresh circuitry, which refresh is monitored by the self refresh test mode controller.

10. The semiconductor device of claim 1, wherein the memory array is a first memory array, the self refresh circuitry is a first self refresh circuitry, and the self refresh test mode controller is a first self refresh controller, and further comprising a second memory array, a second self refresh circuitry, and a second self refresh controller, wherein the second memory array is refreshed in response to the second self refresh circuitry monitored by the second self refresh controller.

11. The semiconductor device of claim 1, wherein the interface includes address lines.

12. The semiconductor device of claim 1, wherein the interface includes DQ lines.

13. The semiconductor device of claim 1, wherein the interface includes lines activated when the self refresh test mode controller is activated.

14. The semiconductor device of claim 1, wherein the selection circuitry is directly responsive to the location refresh signals.

15. The semiconductor device of claim 1, wherein the selection circuitry is indirectly responsive to the location refresh signals.

16. The semiconductor device of claim 1, further comprising a sense amplifier and input/output gating assisting in the performance of the self refresh test mode.

17. The semiconductor device of claim 1, wherein the self refresh circuitry includes a self refresh oscillator and timer.

18. The semiconductor device of claim 1, wherein the self refresh circuitry includes a refresh controller and a refresh counter.

19. The semiconductor device of claim 1, further including a column decoder.

20. The semiconductor device of claim 1, wherein the selection circuitry includes a column decoder.

21. The semiconductor device of claim 1, wherein the refresh signals include signals in addition to the preliminary refresh signals and the location refresh signals, the additional signals controlling various functions of self refresh.

22. The semiconductor device of claim 1, wherein the self refresh circuitry and the self refresh test mode controller are each dedicated hardware.

23. The semiconductor device of claim 1, wherein the self refresh circuitry and the self refresh test mode controller are each included in a microprocessor.

24. The semiconductor device of claim 1, wherein the semiconductor device is a synchronous DRAM.

25. The semiconductor device of claim 1, wherein the semiconductor device is a packetized protocol DRAM.

26. The semiconductor device of claim 1, wherein the semiconductor device is a multi-bank DRAM.

27. A semiconductor device comprising:

an interface allowing connection with an external device;

a memory array;

self refresh circuitry for producing refresh signals including preliminary refresh signals and location refresh signals, with at least some of the preliminary refresh signals being used in producing the location refresh signals during a self refresh test mode;

selection circuitry coupled to the self refresh circuitry and the memory array for selecting memory locations within the memory array to be refreshed in response to the location refresh signals; and

a self refresh test mode controller coupled to the self refresh circuitry and the interface for receiving control signals from the interface and, in response thereto, modifying self refreshing operations of the semiconductor device while it's in the self refresh test mode.

28. A semiconductor device comprising:

an interface allowing connection with an external device;

a memory array;

self refresh circuitry for producing refresh signals including preliminary refresh signals and location refresh signals, with at least some of the preliminary refresh signals being used in producing the location refresh signals;

selection circuitry coupled to the self refresh circuitry and the memory array for receiving the location refresh signals and selecting memory locations within the memory array to be refreshed in response to the location refresh signals; and

a self refresh test mode controller coupled to the self refresh circuitry and the interface for placing the semiconductor device in a self refresh test mode and for receiving control signals from the interface and, in response thereto, modifying performance of the semiconductor device while it's in the self refresh test mode.

29. The semiconductor device of claim 28, wherein the refresh signals include row address strobe signals.

30. The semiconductor device of claim 28, wherein the refresh signals include column address strobe signals.

31. A semiconductor device testing system comprising:

an external testing device; and

a semiconductor device including:

an interface for connection to the external testing device;

a memory array;

self refresh circuitry for producing self refresh signals including preliminary refresh signals and location refresh signals,with at least some of the preliminary refresh signals being used in producing the location refresh signals;

selection circuitry coupled to the self refresh circuitry for selecting memory locations within the memory array to be refreshed in response to the location refresh signals; and

a self refresh test mode controller coupled to self refresh circuitry and the interface for receiving self refresh test control signals from the external testing device through the interface, for controlling self refresh operations of the self refresh circuitry in response thereto, and for transmitting indicating signals to the interface indicative of at least one of the refresh signals, whereby the external testing device analyzes the indicating signals, thereby evaluating the refreshing of the memory array, including a failure in refreshing.

32. The system of claim 31, wherein the indicating signals are indicative of at least some of the preliminary refresh signals and some of the location refresh signals.

33. The system of claim 31, wherein the selection circuitry includes a row decoder and the memory locations are a row of memory locations.

34. The system of claim 31, wherein interaction between the self refresh test mode controller and the self refresh circuitry includes controlling the self refresh circuitry in producing the self refresh signals.

35. The system of claim 31, wherein interaction between the self refresh test mode controller and the self refresh circuitry includes controlling at least some aspect of the self refresh circuitry.

36. The system of claim 31, wherein the semiconductor device is a first semiconductor device, and further including a second semiconductor device substantially identical to the first semiconductor device that is connected to the external testing device, wherein the external testing device tests the first and second semiconductor devices simultaneously.

37. The system of claim 31, wherein the semiconductor device is a first semiconductor device, and further including a second semiconductor device including, in turn, a self refresh test mode controller controlling and monitoring self refresh signals of the second semiconductor device, and the external testing device testing the first and second semiconductor devices substantially simultaneously.

38. A method for testing signals used in self refresh of a memory array of a semiconductor device, the method comprising:

providing self refresh test control signals from an external testing device for controlling a self refresh test mode within the semiconductor device;

producing refresh signals including preliminary refresh signals and location refresh signals in response to the self refresh test control signals, with at least some of the preliminary refresh signals being used in producing the location refresh signals;

selecting memory locations within the memory array to be refreshed in response to the location refresh signals;

interacting with a self refresh circuitry and providing indicating signals indicative of at least one of the refresh signals; and

analyzing the indicating signals, thereby evaluating the self refreshing of the memory array.

39. The method of claim 38, wherein providing indicating signals comprises providing indicating signals indicative of at least some of the preliminary refresh signals and some of the location refresh signals.

40. The method of claim 38, wherein interacting with the self refresh circuitry includes controlling production of the refresh signals.

41. A semiconductor memory comprising:

a memory array;

a self refresh timer for outputting one or more self refresh timing signals during a self refresh test mode of the semiconductor memory;

a self refresh counter coupled to the self refresh timer for outputting row addresses in response to the self refresh timing signals during the self refresh test mode;

a row address buffer coupled to the self refresh counter for buffering the row addresses during the self refresh test mode;

a row decoder coupled to the row address buffer and the memory array for refreshing rows in the array selected in accordance with the row addresses during the self refresh test mode; and

a self refresh test mode controller coupled to at least one of the self refresh timer, the row address buffer, and the row decoder for controlling operation of at least one of the timer, the buffer, and the decoder in outputting the self refresh timing signals, holding the row addresses, and refreshing selected rows in the array in response to self refresh test mode control signals received from an external testing device.

42. A method of testing self refreshing operations of a semiconductor memory, the method comprising:

causing the semiconductor memory to enter a self refresh test mode;

self refreshing the semiconductor memory while it's in the self refresh test mode; and

controlling the self refreshing of the semiconductor memory by providing self refresh test mode control signals to the memory from a testing device external to the memory during the self refresh test mode of the memory.

43. The method of claim 42 wherein the act of causing the semiconductor memory to enter the self refresh test mode comprises causing the semiconductor memory to enter the self refresh test mode using a Row Address Strobe (RAS) signal and a Column Address Strobe (CAS) signal.

44. The method of claim 42 wherein the act of self refreshing the semiconductor memory comprises:

outputting self refresh timing signals from a self refresh timer within the semiconductor memory;

outputting row addresses from a self refresh counter of the semiconductor memory in response to the self refresh timing signals; and

refreshing rows in a memory array of the semiconductor memory selected in accordance with the row addresses using a row decoder of the semiconductor memory.

45. The method of claim 42 wherein the act of controlling the self refreshing of the semiconductor memory comprises controlling at least one of the self refresh timer, the self refresh counter, and the row decoder of the semiconductor memory using the self refresh test mode control signals.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor device having dynamic memory, such as a DRAM device. More particularly, the invention relates to such a semiconductor device that includes a self refresh test mode in which self refresh is monitored and/or modified by an external testing device. The invention also includes a method for constructing such a semiconductor device.

2. State of the Art

DRAMS (dynamic random access memory) include numerous cells in which data are stored. Such cells may include capacitive elements to which a charge is applied to signify a high or low voltage. However, because of leakage, the voltage of the charge decreases over time making the contents of the cells unreliable. Refresh involves reading a datum from a cell before the datum becomes corrupted and rewriting the datum into the cell. The read and rewriting process may be essentially simultaneous.

There are various types of DRAM devices and various types of refresh. DRAMs are often referred to as either "standard refresh" or "extended refresh." Whether a DRAM is a standard refresh or an extended refresh device may be determined by dividing the specified refresh time by the number of cycles. Table 1lists some of the standard DRAMs that have been marketed by Micron Technology, Inc., assignee to the present invention, and their refresh specifications: REFRESH DRAM TIME NO. OF CYCLES REFRESH RATE 4 Meg .times. 1 16 ms 1,024 15.6 .mu.s 256K .times. 16 8 ms 512 15.6 .mu.s 256K .times. 16 64 ms 512 125 .mu.s (L Version) 4 Meg .times. 4 32 ms 2,048 15.6 .mu.s (2K) 4 Meg .times. 4 64 ms 4,096 15.6 .mu.s (4K)

DRAMs having refresh rates of 15.6 .mu.s are standard refresh devices, while DRAMs having refresh rates of substantially greater than 15.6 .mu.s/row are extended refresh devices.

Two basic means of performing refresh are distributed and burst refresh. Distributing the refresh cycles so that they are evenly spaced is known as distributed refresh. When not being refreshed, the DRAM may be read from or written to. In distributed refresh, the DRAM controller is set up to perform a refresh cycle, for example, every 15.6 .mu.s. Usually, this means the controller allows the current cycle to be completed, and then holds off all instructions while a refresh is performed on the DRAM. The requested cycle is then allowed to resume. Refresh may be achieved in a burst method by performing a series of refresh cycles, one right after the other until all rows have been accessed. During refresh, other commands are not allowed.

Different cycles may be used to refresh DRAMs, all of which may be used in a distributed or burst method. Standard refresh types include (1) RAS-ONLY refresh, (2) CAS-BEFORE-RAS (CBR) refresh, and (3) Hidden refresh.To perform a RAS-ONLY refresh, a row address is put on the address lines and then RAS is dropped. When RAS falls, that row will be refreshed and, as long as CAS is held high, the Dqs will remain open.

The DRAM controller provides addresses of cells to be refreshed. The row order of refreshing does not matter as long as each row is refreshed in the specified amount of time.

A CBR refresh cycle is performed by dropping CAS and then dropping RAS. One refresh cycle will be performed each time RAS falls. WE (write enable) is heldhigh while RAS falls. The Dqs will remain open during the cycle. In the case of CBR refresh, an internal counter is initialized to a random count when the DRAM device is powered up. Each time a CBR refresh is performed, the device refreshes a row based on the counter, and then the counter is incremented. When CBR refresh is performed again, the next row is refreshed and the counter is incremented. The counter will automatically wrap and continue when it reaches the end of its count. There is no way to reset the counter. Row addresses are not externally supplied or monitored. CAS is held low before and after RAS falls to meet .sup.t CSR and .sup.t CHR. CAS may stay low and only RAS toggles. Every time RAS falls, a refresh cycle is performed. CAS may be toggled each time, but it is not necessary. The address buffers are powered-down because CBR refresh uses the internal counter and not an external address. For power sensitive applications, this may be a benefit, because there is no additional current used in switching address lines on a bus, nor will the DRAMs pull extra power if the address voltage is at an intermediate state. Because CBR refresh uses its own internal counter, there is not a concern about the controller having to supply the refresh addresses.

In Hidden refresh, the user does a READ or WRITE cycle and then, leaving CAS low, brings RAS high (for minimum of .sup.t RP) and then low. Since CAS was low before RAS went low, the part will execute a CBR refresh. In a READ cycle, the output data will remain valid during the CBR refresh. The refresh is "hidden" in the sense that data-out will stay on the lines while performing the function. READ and Hidden refresh cycles will take the same amount of time: .sup.t RC. The two cycles together take 2.times..sup.t RC. A READ followed with a standard CBR refresh (instead of a Hidden refresh) would take the same amount of time: 2.times..sup.t RC.

A self refresh mode helps maximize power savings in DRAMS and provide a very low-current data-retention mode. Low-power, extended-refresh DRAMs (LPDRAMs) have the same functionality as a standard DRAM, except they have been tested to meet the lower CMOS standby current and the extended refresh specifications. Self refresh DRAMs, on the other hand, require additional circuitry to be added to the standard DRAM to perform the self refresh function.

Self refresh mode provides the DRAM with the ability to refresh itself while in an extended standby mode (sleep or suspend). It is similar to the extended refresh mode of an LPDRAM except the self refresh DRAM utilizes an internally generated refresh clock while in the self refresh mode. During a system's suspend mode, the internally generated refresh clock on the DRAM replaces the DRAM controller refresh signals. Therefore, it is no longer necessary to power-up the DRAM controller while the system is in the suspend mode. Consulting the devices' data sheets will determine the power savings achieved.

Self refresh may employ parameters .sup.t RASS, .sup.t CHD and .sup.t RPS. The DRAM's self refresh mode is initiated by executing a CAS-BEFORE-RAS (CBR) refresh cycle and holding both RAS and CAS LOW for a specified period. The industry standard for this value is 100 .mu.s minimum (.sup.t RASS). The DRAM will remain in the self refresh mode while RAS is LOW. Once CAS has been held LOW for .sup.t CHD, CAS is no longer required to remain LOW and becomes a "don't care."

The self refresh mode is terminated by taking RAS HIGH for .sup.t RPS (the minimum time of an operation cycle). Once the self refresh mode has been terminated, the DRAM may be accessed normally.

Self refresh may be implemented in both a distributed method and a wait and burst method. In a system that utilizes distributed CBR refresh as the standard refresh, accesses to the DRAM may begin as soon as self refresh is exited. The first CBR pulse should occur immediately prior to active use of the DRAM to ensure data integrity. Since CBR refresh is commonly implemented as the standard refresh, this ability to access the DRAM immediately after existing self refresh is a big benefit over the burst scheme described later. If anything other than CBR refresh is used as the standard refresh, a burst of all rows should be executed when exiting self refresh. This is because the CBR counter and the DRAM controller counter will not likely be at the same count. If the CBR counter and the DRAM controller counter are not at the same count and both are being used in the distributed method, then refresh will be violated and data will eventually be lost.

Self refresh may be implemented with an internal burst refresh scheme. Instead of turning on a row at regular intervals, a circuit would sense when the array needs to be refreshed and then sequence through the rows until all had been refreshed. When exiting a burst type self refresh, the entire array must be refreshed before any accesses are allowed, regardless of the type of refresh used. This full burst is necessary because self refresh may have been exited just before the entire array was going to be refreshed. If the burst is not performed when exiting this type of self refresh, the refresh requirements may be violated, leading to lost data.

Some DRAMs allow access to the DRAM as soon as self refresh is exited, while other DRAMs may require a full burst when exiting, regardless of the refresh used. To prevent possible compatibility problems, the controllers are designed to perform the burst when existing self refresh.

FIG. 1. shows a functional block diagram for an exemplary prior art DRAM 10. It will be apparent to those skilled in the art that there are different types of DRAMs and that there is some flexibility in the choice of block diagrams to characterize the DRAM. It will also be apparent that for clarity and simplicity various components and conductors are not shown, but that an understanding of such components and conductors are within the knowledge of those skilled in the art. Accordingly, FIG. 1 is only exemplary. Referring to FIG. 1, data is written to or read from memory locations (or cells) of a memory array 14 through sense amplifier and input/output gating 18, data-in buffer 22 and data-out buffer 24. In ordinary operation, the address of a particular cell to be written to or read from is selected by a row decoder 28 and a column decoder 34 under the direction of addresses A0-A9, which are processed by row address buffers 38 and column address buffers 40. DRAM 10 may include a complement select and row select circuit between row decoder 28 and array 14.

A RAS signal is received by a clock generator 44 which in response thereto supplies the RAS signal to a refresh controller and self refresh oscillator and timer 64. Clock generator 44 also supplies clock signals to sense amp and input/output gating 18, row decoder 28, a clock generator 48. A CAS signal is supplied to control logic 56, a clock generator 48, column address buffers 40, and refresh controller and self refresh oscillator and timer 64. A write enable WE signal and an output enable OE signal are also received by control logic 56. Control logic 56 controls data-in buffer 22 and data-out buffer 24 based on the state of CAS, WE, and OE, and a clock signal from clock generator 48, according to well known protocols.

In self refresh mode, refresh controller and self refresh oscillator and timer 64 and a refresh counter 66 control the row address of the cell to be refreshed, while the column cells are refreshed simultaneously.

There may be difficulties in testing DRAM devices that incorporate self refresh mode if the failures are present during self refresh operation. This complication may result because the external testing device no longer has control of internal DRAM clock signals such as RAS and CAS. Once the self refresh mode is entered, the DRAM internally times the necessary clock signals, and the external signals are ignored, except for external RAS which is used to terminate self refresh. A difficult test problem is encountered when a device failure occurs related to self refresh. In other failure modes, it is possible to vary timing to determine sensitivities of the failure to aid in troubleshooting the problem. In some cases, the failure is related to the period of the cycle the DRAM is in when self refresh is exited.

Prior systems have been proposed to provide signals indicative of the operations of a DRAM during self refresh. For example, U.S. Pat. No. 5,450,364 to Stephens, Jr. et al. describes a system the purpose of which is to create significant time savings in testing self refresh operation. The system is purported to generate a signal upon completion of the self refresh cycle, thus allowing a fast determination of whether the self refresh cycle has been completed within the pause time of the memory part. U.S. Pat. No. 5,418,754 to Sakakibara describes a system in which a self refresh cycle time is purported to be directly measured at a data output pin. U.S. Pat. No. 5,299,168 to Kang proposes a semiconductor memory circuit having a refresh address test circuit for detecting whether all of the refresh addresses have been generated.

However, these prior systems do not allow an external testing device to have general access to internal signals such as RAS, CAS, or other timing signals during self refresh.

Accordingly, there remains a need for a memory device such as a DRAM that contains circuitry that allows an external testing device to have general access to internal signals of the memory device, as well as provide external control or modification of the self refresh cycle while in a test mode.

SUMMARY OF THE INVENTION

The present invention relates to a semiconductor device having dynamic memory, and a system and method for testing self refresh functions of the semiconductor device. The semiconductor device may include an interface for connection with an external device such as a testing device, that may supervise the testing of the self refresh functions and analyze information transmitted from the semiconductor device regarding the refresh. Information regarding the testing may be transmitted to the external testing device in real time or after the conclusion of the testing. Alternatively, the testing may be done internally without the aid of the external tester. However, information regarding the testing would be transmitted to an external device, in real time or otherwise.

The semiconductor device may include self refresh circuitry, selection circuitry, and a self refresh test mode controller.

The self refresh circuitry may produce refresh signals including preliminary refresh signals and location refresh signals. At least some of the preliminary signals are used in producing the location refresh signals. Still other refresh signals may control various aspects of self refresh, such as communicating with the circuits in the semiconductor device or with the external device. The self refresh circuitry may include a refresh controller and a refresh counter.

The selection circuitry may receive the location refresh signals and select memory locations within the memory array to be refreshed according to the values of the location refresh signals. The memory of the semiconductor device may be a memory array having rows and columns. The memory locations selected by the selection circuitry may be rows. The memory location selecting circuitry may be directly or indirectly responsive to the location refresh signals.

The self refresh test mode controller may interact with the self refresh circuitry and transmits indicating signals to the interface that are indicative of at least one of the refresh signals. The indicating signals may be indicative of some or all of the preliminary refresh signals, some or all of the location refresh signals, or other refresh signals. The preliminary refresh signals may include row address strobe signals and/or column address strobe signals. The external testing device may analyze the indicating signals to evaluate the refreshing of the memory array, including a failure in refreshing.

The self refresh test mode controller provides at least one or more of the following four functions: the ability to control internal signals while in self-refresh mode; the ability to monitor internal signals while in self-refresh mode; the abi