Semiconductor device with metal-oxide conductors

What is claimed is:

1. A semiconductor device comprising:

a wiring having a laminated structure comprising a first wiring layer comprising a first metal film and a second wiring layer comprising a second metal film formed on said first wiring layer,

wherein said wiring comprises a first oxide film of said first metal film formed in contact with a side surface of said first wiring layer, and a second oxide film of said second metal film formed in contact with a side surface of said second wiring layer.

2. A semiconductor device comprising:

a wiring having a laminated structure comprising a first wiring layer comprising a first metal film and a second wiring layer comprising a second metal film formed on said first wiring layer,

wherein said wiring comprises a first oxide film formed by oxidizing said first wiring layer and a second oxide film formed by oxidizing said second wiring layer, and

wherein a lower part of said second wiring layer is in contact with only said first wiring layer and a lower part of said second oxide film is in contact with said first wiring layer and said first oxide film.

3. A semiconductor device comprising:

a wiring having a laminated structure comprising a first wiring layer comprising a first metal film and a second wiring layer comprising a second metal film formed on said first wiring layer,

wherein said wiring comprises a first oxide film formed by oxidizing said first wiring layer and a second oxide film formed by oxidizing said second wiring layer, and

wherein an interface between said second wiring layer and said second oxide film is present inside an interface between said first wiring layer and said first oxide film.

4. A semiconductor device as claimed in claim 2 or 3, wherein a film thickness of said first oxide film present under said second oxide film gradually increases toward the outside.

5. A semiconductor device as claimed in claims 2 or 3, wherein said first oxide film extends outside a side surface of said second oxide film.

6. A semiconductor device as claimed in claims 2 or 3, wherein

said first oxide film extends outside a side surface of said second oxide film; and

a thickness of said first oxide film under said second oxide film is different from that outside a side surface of said second oxide film.

7. A semiconductor device as claimed in claims 2 or 3, wherein

said first oxide film extends outside a side surface of said second oxide film; and

said first oxide film has a part, at which a film thickness thereof becomes maximum, outside a side surface of said second oxide film.

8. A semiconductor device as claimed in claim 2 or 3, wherein

said first oxide film extends outside a side surface of said second oxide film;

said first oxide film has a part, at which a film thickness thereof becomes maximum, outside a side surface of said second oxide film; and

said first oxide film has a region, in which a film thickness thereof is substantially constant, outside said part, at which said film thickness becomes maximum.

9. A semiconductor device as claimed in claim 2 or 3, wherein

said first oxide film extends outside a side surface of said second oxide film;

said wiring overlaps a semiconductor layer comprising silicon of at least one of an insulated gate type transistor; and

on one of said semiconductor layer, said first oxide film has a part, at which a film thickness thereof becomes maximum, outside a side surface of said second oxide film.

10. A semiconductor device as claimed in claim 2 or 3, wherein

said first oxide film extends outside a side surface of said second oxide film;

said wiring overlaps a semiconductor layer comprising silicon of at least one of an insulated gate type transistor; and

on at least one of said semiconductor layer, said first oxide film has a part, at which a film thickness thereof becomes maximum, outside a side surface of said second oxide film, and has a region, in which said film thickness becomes substantially constant, outside said part, at which said film thickness becomes maximum.

11. A semiconductor device as claimed in claim 2 or 3, wherein

said first oxide film extends outside a side surface of said second oxide film;

said first oxide film has a part, at which a film thickness thereof becomes maximum, outside a side surface of said second oxide film, and

said film thickness at said part, at which said film thickness becomes maximum, is 2 times to 4 times a thickness of said first wiring layer.

12. A semiconductor device as claimed in one of claim 2 or 3, wherein

said first oxide film extends outside a side surface of said second oxide film;

said first oxide film has a part, at which a film thickness thereof becomes maximum, outside a side surface of said second oxide film;

said first oxide film has a region, in which a film thickness thereof is substantially constant, outside said part, at which said film thickness becomes maximum; and

said film thickness in said region, in which said film thickness becomes substantially constant, is 2 times to 4 times a thickness of said first wiring layer.

13. A semiconductor device as claimed in claim 2 or 3, wherein

said wiring is formed on an insulating film in an island form; and

said side surface of said first oxide film substantially agree with a side surface of said insulating film in an island form.

14. A semiconductor device comprising:

a plurality of insulating gate transistors, each having a gate wiring having a laminated structure comprising a first wiring layer comprising a first metal film and a second wiring layer comprising a second metal film formed on said first wiring layer,

wherein said gate wiring comprises a first oxide film formed by oxidizing said first wiring layer and a second oxide film formed by oxidizing said second wiring layer,

wherein said first oxide film extends outside said second oxide film, and

wherein an interface between said second wiring layer and said second oxide film is present inside an interface between said first wiring layer and said second oxide film.

15. A semiconductor device as claimed in claim 14, wherein each of said insulating gate transistors has a semiconductor layer comprising silicon, said semiconductor layer comprising a low concentration impurity region formed in a region, on which only said first oxide film is present via a gate insulating film.

16. A semiconductor device as claimed in claim 14, wherein each of said insulating gate transistors has a semiconductor layer comprising silicon, and wherein said first oxide film extends outside said second oxide film in a transverse direction of a channel with respect to said semiconductor layer.

17. A semiconductor device as claimed in claim 2, 3 or 14, wherein said first oxide film is provided by subjecting said first metal film to anodic oxidation, and said second oxide film is provided by subjecting said second metal film to anodic oxidation.

18. A semiconductor device as claimed in claim 2, 3 or 14, wherein said first metal film and said second metal film are different in anodic oxidation rate from each other.

19. A semiconductor device as claimed in claim 2, 3 or 14, wherein said first metal film and said second metal film are different in anodic oxidation rate from each other, and wherein said first oxide film and said second oxide film are provided by the same anodic oxidation step.

20. A semiconductor device as claimed in one of claim 2, 3 or 14, wherein said first metal film has a film thickness of from 1 to 50 nm.

21. A semiconductor device as claimed in claim 2, 3 or 14, wherein said second metal film comprises aluminum or a material mainly comprising aluminum.

22. A semiconductor device as claimed in claim 2, 3 or 14, wherein said first metal film comprises a valve metal.

23. A semiconductor device as claimed in claim 2, 3 or 14, wherein said first metal film comprises a material mainly comprising one selected from Ta, Nb, Hf, Ti and Cr, or an alloy containing these elements.

24. A semiconductor device as claimed in claim 2, 3 or 14, wherein said first metal film comprises tantalum or a material mainly comprising tantalum.

25. A semiconductor device as claimed in claim 1, 2, 3 or 14, wherein said semiconductor device is one of an active matrix type liquid crystal display and an active matrix type EL display.

26. A semiconductor device as claimed in claim 1, 2, 3 or 14, wherein said semiconductor device is one selected from the group consisting of a personal computer, a video camera, a goggle type display, a player apparatus, a digital camera, a front type projector and a rear type projector.

27. A semiconductor device comprising a bottom gate type thin film transistor, comprising:

a gate wiring having a laminated structure comprising a first wiring layer comprising a first conductive film and a second wiring layer comprising a second conductive film formed on said first wiring layer;

a first oxide film provided by oxidizing said first wiring layer; and

a second oxide film provided by oxidizing said second wiring layer,

wherein a lower part of said second wiring layer is in contact with only said first wiring layer, and wherein a lower part of said second oxide film is in contact with said first wiring layer and said first oxide film.

28. A semiconductor device comprising a bottom gate type thin film transistor, comprising:

a gate wiring having a laminated structure comprising a first wiring layer comprising a first conductive film and a second wiring layer comprising a second conductive film formed on said first wiring layer;

a first oxide film provided by oxidizing said first wiring layer; and

a second oxide film provided by oxidizing said second wiring layer,

wherein an interface between said second wiring layer and said second oxide film is present inside an interface between said first wiring layer and said first oxide film.

29. A semiconductor device as claimed in claim 27 or 28, wherein said first oxide film extends outside a side surface of said second oxide film.

30. A semiconductor device as claimed in claim 27 or 28, wherein said first oxide film has a film thickness 2 times to 4 times a thickness of said first wiring layer.

31. A semiconductor device as claimed in claim 27 or 28, wherein said first conductive film and said second conductive film are different in anodic oxidation rate from each other.

32. A semiconductor device as claimed in claim 27 or 28, wherein said first conductive film and said second conductive film are different in anodic oxidation rate from each other, and wherein said first conductive film and said second conductive film are provided by the same anodic oxidation step.

33. A semiconductor device as claimed in claim 27 or 28, wherein said first conductive film has a film thickness of from 1 to 50 nm.

34. A semiconductor device as claimed in claim 27 or 28, wherein said second conductive film comprises aluminum or a material mainly comprising aluminum.

35. A semiconductor device as claimed in claim 27 or 28, wherein said first conductive film comprises a valve metal.

36. A semiconductor device as claimed in claim 27 or 28, wherein said first conductive film comprises a material mainly comprising one selected from Ta, Nb, Hf, Ti and Cr, or an alloy containing these elements.

37. A semiconductor device as claimed in claim 27 or 28, wherein said first conductive film comprises tantalum or a material mainly comprising tantalum.

38. A semiconductor device as claimed in claim 27 or 28, wherein said first conductive film comprises tantalum or a material mainly comprising tantalum, and wherein said first conductive film comprises at least one layer comprising tantalum containing nitrogen.

39. A semiconductor device as claimed in claim 27 or 28, wherein said semiconductor device is one of an active matrix type liquid crystal display and an active matrix type EL display.

40. A semiconductor device as claimed in claim 27 or 28, wherein said semiconductor device is one selected from the group consisting of a personal computer, a video camera, a goggle type display, a player apparatus, a digital camera, a front type projector and a rear type projector.

Description Submit all comments and votes

FIELD OF THE INVENTION

The present invention relates to a structure production process of a semiconductor device such as a insulated gate type transistor having wiring formed with an aluminum material. The semiconductor device of the invention includes not only a device such as a thin film transistor and a MOS transistor but also an electronic apparatus, such as a display apparatus and an image sensor, having a semiconductor circuit constituted with such an insulated gate type transistor.

BACKGROUND OF THE INVENTION

In recent years, an active matrix type liquid crystal display having a pixel area and a driving circuit constituted with a thin film transistor (hereinafter abbreviated as TFT) formed on a substrate having an insulating property receives attention. A liquid crystal display includes one having a size of from 0.5 to 2 inches for a projection display and one having a size of from 10 to 20 inches for a portable computer, and is used as a display device of a small size to a middle size.

In recent years, a liquid crystal display having a large area is being demanded. In a liquid crystal display of a large area, the area of a pixel matrix area as an image display part becomes large, and thus source wiring and gate wiring arranged in a matrix form become long, which results in increase in wiring resistance. The wiring should be thin due to a demand of minuteness, and the increase in wiring resistance is tangible. Furthermore, since the source wiring and the gate wiring are connected to a TFT for each pixel, and there arises a problem of increase in parasitic capacity. In a liquid crystal display, since gate wiring and a gate electrode are unitedly formed, delay of a gate signal becomes tangible along with increase in area of the panel.

Accordingly, a material mainly comprising aluminum having a relatively low resistance is used as the gate wiring. By forming the gate wiring and the gate electrode with a material mainly comprising aluminum, the gate delay time can be lowered, and the device can be operated at a high speed.

An attempt of decreasing an off current has been conventionally made by making a thin film transistor having an offset structure or an LDD (light doped drain) structure. In Japanese Patent No. 2,759,415, the inventors propose a thin film transistor of an LDD structure. The Japanese Patent No. 2,759,415 corresponds to a U.S. Pat. No. 5,648,277. The Japanese Patent No. 2,759,415 and the U.S. Pat. No. 5,648,277 disclose a process for forming an LDD structure in a semiconductor layer in a self alignment manner by using aluminum as a gate electrode material and subjecting the gate electrode to anodic oxidation. The process will be described with reference to FIGS. 38A to 38E. An entire disclosure of the Japanese Patent No. 2,759,415 and the U.S. Pat. No. 5,648,277 is incorporated herein by reference.

An underlayer film 1011, such as a silicon oxide film, is formed on a glass substrate 1010. An active layer 1013 comprising a polycrystalline silicon film is formed on the underlayer film 1011,and a gate insulating film 1014 is formed on the active layer 1013. An aluminum film is formed and patterned by using a photoresist mask 1016 to form a gate electrode 1015 comprising aluminum. (FIG. 38A)

The pattern is subjected to anodic oxidation in an electrolytic solution by using the gate electrode 1015 as an anode to form a porous alumina film 1017. In this stage, since the surface of the gate electrode 1015 is covered with the mask 1016, the alumina film 1017 is formed only on the side surface of the gate electrode 1015. (FIG. 38C)

After removing the photoresist mask 1016, the gate electrode 1015 is again subjected to anodic oxidation to form a non-porous alumina film 1018. (FIG. 38B)

The gate insulating film 1014 is patterned by using the alumina films 1017 and 1018 as a mask. (FIG. 38D) The porous alumina film 1017 is then removed.

After obtaining this state, the active layer 1013 is doped with an impurity endowing an n-type or p-type conductivity by a plasma doping method. The doping is conducted as divided into two stages. The first stage is conducted at such low acceleration that the gate insulting film 1014 functions as a mask with a large dose amount. The second stage is conducted at such high acceleration that the impurity passes through the gate insulating film 1014 with a small dose amount. As a result, a channel forming region 80, a source region 81, a drain region 82 and low concentration impurity regions 93 and 84 are formed in the active layer 1013 in a self alignment manner. The low concentration impurity region 84 in the side of the drain region 82 is the LDD region.

However, in order to conduct the anodic oxidation treatment, all the electrodes and wiring to be subjected to anodic oxidation should be connected to voltage supplying wiring for anodic oxidation. For example, in the case where the technique disclosed in the literature described above is applied to an active matrix type liquid crystal panel, the gate electrodes and wiring of the thin film transistor constituting the active matrix area and the driver circuit should be connected to voltage supplying wiring. In order to make such a connection, voltage supplying wiring is formed on the substrate, which results in increase of the area of the substrate.

Each gate electrode and gate wiring forms a short circuit with the voltage supplying wiring, and after the anodic oxidation treatment, unnecessary connected parts to the supplying wiring are removed by etching to separate the respective gate wiring and gate electrodes. Therefore, the circuit should be designed with consideration of a process margin of the etching process.

Accordingly, in order to produce a transistor by using the anodic oxidation treatment, additional area for forming the voltage applying wiring and the etching margin are required, which become a bar to the production of a highly integrated circuit and the decrease in area of the substrate.

Furthermore, since aluminum is used as the material of the gate electrode 1015 in the literature described above, the alumina film 1018 is made of alumina. Therefore, the alumina film should be etched in order to connect the gate wiring and the leading wiring. The inventors have used buffered hydrofluoric acid (a mixed solution of ammonium fluoride and hydrofluoric acid) is used as an etchant on the etching.

However, the buffered hydrofluoric acid is low in selectivity between alumina (representative example thereof is Al.sub.2 O.sub.3) and aluminum, and thus there is a problem in that it etches not only the alumina film but also the gate wiring thereunder. The problem will be described with reference to FIG. 39.

In FIG. 39, numeral 1031 denotes a substrate having an insulating surface, 1032 denotes an insulating film comprising silicon oxide (which functions as a gate insulating film on the active layer), 1033 denotes gate wiring comprising aluminum, 1034 denotes an alumina (anodic oxidized) film obtained by subjecting the gate wiring 1033 to anodic oxidation.

When a part of an upper surface of the alumina film 1034 is etched with the buffered hydrofluoric acid, the gate wiring 1033 is firstly exposed. In general, since the etching is conducted with a certain distribution within the surface of the substrate, it is necessary to completely remove the alumina film 1034 by over-etching.

At this time, when the over-etching is excessively conducted, the gate wiring 1033 is etched by the buffered hydrofluoric acid. There is a possibility that an etching hole 1035 reaches the insulating film 1032 through the gate wiring 1033.

When such a situation is developed, the gate wiring 1033 is connected to the leading line (not shown in the figure) only on a cross section 1036 (expressed by thick lines) of the gate wiring 1033. Because the diameter of the general contact hole is several micrometers, whereas the film thickness of the gate wiring is several hundreds nm, the area on which the gate wiring and the leading line are in contact with each other becomes smaller by about 1/100 than the ordinary case at the state as shown in FIG. 39.

That is, when the situation of FIG. 39 is developed, the contact area of the wiring is extremely decreased to make conditions in that electric contact is impossible. Therefore, the TFT is difficult to be operated, which brings about malfunctioning of the circuit.

When the situation is developed in a structure, in which an active layer of a TFT is present under the insulating film 1032 (for example, contact between the gate electrode and the leading line is made on the TFT), there may be the case in that the leading line and the active layer form a short circuit.

The inventors have then developed a process in that a special etchant is used instead of the buffered hydrofluoric acid. The etchant used by the inventors is an etchant obtained by mixing 10 liter of a solution obtained by mixing phosphoric acid, nitric acid, acetic acid and water in a ratio of 85/5/5/5 with 550 gram of a chromic acid solution (300 gram of chromic acid and 250 gram of water). The inventors call the solution as a chromic mixed acid.

The chromic mixed acid has selectivity in that it etches an alumina film as an anodic oxide film but does not etch an aluminum film. The selective etching of the alumina film can be conducted by using the property of the chromic mixed acid. At present, a contact hole for connecting the gate electrode and the leading line is formed by using such a special etchant. This method realizes a high yield and a good ohmic contact.

However, the method using the chromic mixed acid is not industrially preferred because a large amount of chromium is used, which is a heavy metal that may cause damage to a human body. While development of a substitute etchant is earnestly conducted because of such reasons, a satisfactory etchant has not yet developed at present.

In a TFT using an aluminum material as wiring, when the process temperature after the formation of aluminum wiring is from 300 to 450.degree. C., malfunction of the TFT is confirmed. Various factors can be considered as reasons of the malfunction. In particular, many reasons of the malfunction of a TFT are caused by a short circuit between the gate electrode and the channel formed by a protruded matter, such as hillock and whisker, reaching the channel forming region through the gate insulating film, and an aluminum atom being diffused into the gate insulating film.

When aluminum is heated to a temperature of about 400.degree. C. hillock is formed on the surface, and an aluminum atom is diffused. Therefore, the heat resistance of aluminum is increased by adding Si and Sc or by subjecting the gate wiring to anodic oxidation to cover an anodic oxide product. In a bottom gate type TFT, the gate wiring must be covered with an anodic oxide film to resist against the film formation temperature of the gate insulating film of from 300 to 450.degree. C.

However, in order to conduct the anodic oxidation treatment, all the electrodes and wiring to be subjected to anodic oxidation must be connected to voltage supplying wiring for anodic oxidation. For example, in the case where the technique disclosed in the literature described above is applied to an active matrix type liquid crystal panel, the gate electrodes and wiring of the thin film transistors constituting the active matrix area and the driver circuit must be connected to the voltage supplying wiring. In order to make such a connection, the voltage supplying wiring is formed on the substrate, which results in increase of the area of the substrate.

Each gate electrode and gate wiring forms a short circuit with the voltage supplying wiring, and after the anodic oxidation treatment, unnecessary connected parts to the supplying wiring are removed by etching to separate the respective gate wiring and gate electrodes. Therefore, the circuit should be designed with consideration of a process margin of the etching process.

Accordingly, in order to produce a transistor by using the anodic oxidation treatment, additional area for forming the voltage applying wiring and the etching margin are required, which become a bar to the production of a highly integrated circuit and the decrease in area of the substrate.

Furthermore, a high mobility is demanded in a TFT at present, and a highly crystalline silicon film receives attention as an active layer since it has a higher mobility than an amorphous silicon film. Conventionally, a quartz substrate having a high strain point must be used to obtain a crystalline silicon film by a heat treatment. Since the quartz substrate is expensive, a crystallization technique using an inexpensive glass substrate is being developed.

A technique of lowering the crystallization temperature has been disclosed by the inventors in JP-A-6-232059 and JP-A-7-321339. The JP-A-6-232059 corresponds to a U.S. Pat. No. 5,843,225. An entire disclosure of the JP-A-6-232059, the JP-A-7-321339 and the U.S. Pat. No. 5,843,225 is incorporated herein by reference. In the technique, a slight amount of a metallic element is introduced into an amorphous silicon film, which is then subjected to a heat treatment, to obtain a crystalline silicon film. As the metallic element accelerating the crystallization, at least one selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu and Au is employed. By using this technique, a crystalline silicon film can be produced at a process temperature, to which the glass substrate can resist.

However, the technique involves a problem in that the metallic element used for crystallization remains in the crystalline silicon film, which may be a cause of deterioration of the reliability and uniformity in characteristics of the TFT. The inventors have then developed a technique in that after forming wiring by using an aluminum material, the metallic element contained in the crystalline silicon film is gettered (JP-A-8-330602). An entire disclosure of the JP-A-8-330602 is incorporated herein by reference. In this technique, a heat treatment is conducted by using the source/drain region as a gettering sink, and thus the metallic element contained in the channel forming region is gettered to the source/drain region.

However, since the gettering technique described above employs an aluminum material having a low heat resistance as wiring, only the heat treatment at a temperature range of about from 300 to 450.degree. C. is conducted. The heating temperature of from 300 to 450.degree. C. is too low to sufficiently conduct gettering of the metallic element contained in the crystalline silicon film, and a treatment for a long period of time is necessary. Therefore, the short circuit between the gate electrode and the channel described above is liable to occur.

As a method for forming the crystalline silicon film, a method for forming a polycrystalline silicon film by as-depo, and a method for crystallizing an amorphous silicon film by a heat treatment or irradiation with laser light have been known.

In the case of a bottom gate type TFT, the gate wiring is formed before the formation of the active layer. Therefore, a crystallization process using an excimer laser is preferred for making small the influence of heat to the gate wiring. In the case where an aluminum material is used as the gate wiring, even when the laser crystallization process is employed, and the heat resistance is increased by the anodic oxidized film, there may be the case where the gate wiring is deformed due to the formation of a protruded matter, such as hillock and whisker, on aluminum.

As described in the foregoing, the uses of an aluminum material for wiring from the standpoint of wiring resistance, but various problems arise by using the aluminum material. The problems are summarized below.

First, a thin film transistor having an LDD structure can be produced in a self alignment manner by using the anodic oxidation technique. However, because voltage supplying wiring for anodic oxidation must be formed, high integration of the circuit and decrease in area of the substrate are inhibited.

Second, in a process for forming a contact hole for a leading electrode of a gate electrode, the use of the chromic mixed acid is unavoidable for removing alumina covering the gate electrode.

Third, because of the low heat resistance of aluminum, a short circuit is formed between gate wiring and a channel, to cause malfunction of the TFT.

Furthermore, in a bottom gate type TFT, the gate wiring is formed before the crystallization process of the silicon film. In the total process, the crystallization process is one applying the largest heat influence to the gate wiring. Even when a laser crystallization process applying a relatively small heat influence is employed, and the aluminum layer is covered with the anodic oxide film, it is difficult to completely prevent deformation (blister) of the gate wiring due to the formation of hillock.

SUMMARY OF THE INVENTION

The invention relates to a semiconductor device having a novel wiring structure that solves the problems described above at a stroke.

In the invention, the anodic oxidization of an aluminum material is conducted without forming voltage supplying wiring for anodic oxidation. Furthermore, a first wiring comprising a laminated structure of alumina and aluminum, and good ohmic contact between the first wiring and a second wiring electrically contacting with the first wiring are realized without using the chromic mixed acid, and a short circuit between the gate electrode and the channel is prevented.

In order to solve the problems described above, the invention relates to a semiconductor device having wiring comprising a laminated structure comprising a first wiring layer comprising a first conductive film having laminated thereon a second wiring layer comprising a second conductive film, wherein the wiring comprises a first oxide film formed by oxidizing the first wiring layer, and a second oxide film formed by oxidizing the second wiring layer; a lower part of the second wiring layer is in contact only with the first wiring layer; and a lower part of the second oxide film is in contact with the first wiring layer and the first oxide film.

One of the characteristic features of the invention resides in the wiring having the multi-layer structure, in which diffusion of the material constituting the second wiring layer is prevented by the first wiring layer. Therefore, the upper limit of the process temperature after the formation of the gate wiring can be increased. Another characteristic feature of the invention is to conduct anodic oxidation of the first and second wiring layers without forming voltage supplying wiring for anodic oxidation. Accordingly, by using the first conductive film constituting the first wiring layer as the wiring for anodic oxidation, anodic oxidation of the second wiring layer is realized.

The path to the invention will be described with reference to FIGS. 35A to 35E, 36A to 36C, 37A to 37C and 38A to 38E.

The inventors have confirmed as to whether or not plural aluminum patterns formed on a tantalum film by patterning to an island form can be subjected to anodic oxidation by using the tantalum film as an electrode. FIGS. 35A to 35E are cross sectional views showing the aluminum pattern in each steps of the experiment. FIGS. 36A to 36C are partial enlarged cross sectional view of FIGS. 35C to 35E. FIGS. 37A to 37C are SEM (Scanning Electron Microscope) photographs obtained by observing the cross sectional structures in FIGS. 36A to 36C.

The experiment was conducted in the following manner.

A tantalum (Ta) film 41 having a thickness of 20 nm and an aluminum (Al) film 42 having a thickness