A method and system of monitoring code as it is executed by a target processor is provided for debugging, etc. Standardized software code function preamble and postamble instructions are dynamically replaced with instructions that will generate a predetermined exception. The exception generates a branch to a conventional exception vector table. An exception routine is inserted into the vector table, and includes instruction(s) to disable the data and/or address caches. Subsequent instructions in the vector table execute the replaced preamble instruction and, with or without re-enabling the cache, branch back to the address of the program code immediately following the faulted preamble address. Instructions of the function executed while cache is disabled are executed on the bus where they are visible, as opposed to within cache.
A method and system for reverting a process in an in-line instrumented state to an uninstrumented state. In one embodiment, the present invention modifies selected text segment portions from the process to be uninstrumented. The present embodiment then unmaps instrumented code space such that the instrumented code space is inaccessible to the process. In this embodiment, provided an instruction pointer resides in the instrumented code space, the present invention updates the instruction pointer to uninstrumented code space. The present embodiment also executes the process and, provided the process generates a fault by seeking to access an address in instrumented code space, provides a corresponding address in uninstrumented code space. In one embodiment, the present invention then continues execution at the address in instrumented code space.
A system includes at least one memory operable to store a first flag identifying whether a cache is disabled and a second flag identifying whether use of the cache is blocked. The system also includes combinatorial logic operable to use the first and second flags to determine whether the cache is used during execution of at least one instruction by a processor. The first flag identifies that the cache is enabled and the second flag identifies that the use of the cache is blocked when the processor is operating in a debugging mode.
The present invention, in various embodiments, is directed to techniques for providing debugging capability for program code instrumentation. In one embodiment, an instrumentor inserts an instrumentation breakpoint at the beginning of a block of original code. When this breakpoint is reached during execution of the application program that includes the block of original code, the instrumenator, from the block of original code, generates a block of instrumented code. This block of instrumented code may include debugging breakpoints that are carried from the block of original code or are inserted into the block of instrumented code during debugging. After generating the instrumented code, the instrumentor executes the instrumented code until debugging breakpoints are reached that stop the program flow, thereby allowing a programmer to perform debugging functions at these debugging breakpoints.
A method, apparatus and computer instructions for handling exception vectors by firmware. An exception vector is identified to form an identified exception vector when control is passed from an operating system to the firmware. The identified exception vector is saved to form a saved exception vector. The identified exception vector is then replaced with a substitute vector; and the saved exception vector is restored when control is returned to the operating system to form a restored exception vector. At that point, the restored exception vector is again used to perform error and debugging processes.
There is provided a method for employing a trigger point in a logic flow. The trigger point has at least one function associated therewith. A default strategy set is associated with the at least one function of the trigger point. The default strategy set has a capability of being replaced, in whole or in part, by a non-default strategy set. The strategy sets are for implementing the at least one function of the trigger point. The trigger point is dynamically configured, including establishing at least one context for the trigger point that respectively specifies a location of the strategy sets. The trigger point is executed when encountered during an execution of the logic flow, including selectively executing at least a portion of at least one of the default strategy set and the non-default strategy set based upon a current context from among the at least one context.
