An interleaved small-inductance buck voltage regulator (VRM) converter with the novel current sensing and sharing technology significantly improves transient response with size minimization. Specifically, two or more buck VRM modules are interleaved or connected in parallel. The resultant current waveform has a fast transient response but with reduced ripples since the ripples in the individual modules mathematically cancel one another. The result is a smooth output current waveform having spikes within an acceptable tolerance limits when for example the load increases due to a connected processor changing from "sleep" to "active" mode. A novel current sensing and sharing scheme between the individual VRMs is implemented using an RC network in each module to detect inductor current for that module. Good current sharing result can be easily achieved. Unlike peak current mode control and average current mode control, with this technology, the converter still has low output impedance and fast transient response. As a result, the VRM can be very cost-effective, high power density, high efficiency and have good transient performance.
CROSS REFERENCE TO RELATED APPLICATION
This application is a continuation of application Ser. No. 09/448,297, filed on Nov. 24, 1999, now abandoned, which claims priority to provisional application Serial No. 60/110,694, filed on Dec. 3, 1998, both of which are herein incorporated by reference.
In order to control a converter (1) which is used to convert a primary input voltage (U.sub.E) into a secondary output voltage (U.sub.a), a voltage value (U.sub.v) derived from a secondarily detected real voltage (U.sub.ist) is compared with a reference value (U.sub.R), and a control signal (S.sub.a) is produced as a criterion which triggers the disconnection of said converter (1) if said reference value is exceeded. The voltage value (U.sub.v) or the reference value (U.sub.R) is manipulated during a monitoring phase in such a way that said parameter is met.
A buck converter includes a first transistor, a second transistor, a filter circuit, a capacitor and a switch. The first transistor has a drain for receiving a first DC voltage, a gate for receiving a first control signal, and a source coupled to a node. The second transistor has a drain coupled to the node, a gate for receiving a second control signal, and a source coupled to a constant voltage. The filter circuit is electrically coupled to the node for outputting a second DC voltage. The switch has a first terminal electrically coupled to the gate of the second transistor via the capacitor, a second terminal electrically coupled to the source of the second transistor, and a control terminal for receiving the first control signal. The switch has a faster switching speed than the first transistor.
A shunt voltage regulator for a processor is disposed on the processor package. The shunt voltage regulator responds to AC transients. One embodiment includes a DC power converter voltage regulator that is disposed off the processor package, and that is optimized for DC power conversion. Another embodiment includes a method of improving fabrication yield for a packaged processor.
A system and method are provided for actively reducing ripple in a supply voltage provided by a switched mode power supply. In general, active ripple reduction circuitry operates to sense the ripple in the supply voltage to provide a signal indicative of the ripple. The signal indicative of the ripple is inverted and provided to the output of the switched mode power supply to substantially reduce or eliminate the ripple in the supply voltage.
A shunt voltage regulator for a processor is disposed on the processor package. The shunt voltage regulator responds to AC transients. One embodiment includes a DC power converter voltage regulator that is disposed off the processor package, and that is optimized for DC power conversion. Another embodiment includes a method of improving fabrication yield for a packaged processor.
