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Analog to digital converter having a parallel converter and logic for generating serial data
   
Document Number
US Patent 6414621
Issued Date
July 2, 2002
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Abstract
An analog to digital converter (ADC) circuit suitable for processing serial data at a fast rate includes a clock control block for receiving a reference strobe signal REF_STB, a reference clock signal REF_CLK, and number of bit control signals CONT.sub.-- 1, CONT.sub.-- 2. The clock control block outputs first and second internal clock signals CLK_A, and CLK_B, and a forwarding direction control signal CONT.sub.-- 3. The ADC circuit also includes a parallel analog to digital converter for receiving and converting analog signal into a parallel digital data synchronously with the first internal clock signal CLK_A. A parallel to serial transform logic control block then transforms the parallel digital data into serial digital data synchronously with the second internal clock signal CLK_B.
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Analog to digital converter having a parallel converter and logic for generating serial data - US Patent 6414621 Drawing
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Number of Claims:
7
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Published
July 2, 2002
Application Number
09/704,752
Filed
November 3, 2000
US Classification
341/159   341/123
Int'l Classification
H03M   9/00   (20060101)   H03M   1/36   (20060101)  
Examiner
Priority Data
Nov 04, 1999 [KR] 99-48613
USPTO Field of Search
341/155   341/131   341/110   341/59   341/159   341/123   710/21   360/32  
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