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High performance packaging for microprocessors and DRAM chips which minimizes timing skews    
United States Patent6424034   
Link to this pagehttp://www.wikipatents.com/6424034.html
Inventor(s)Ahn; Kie Y. (Chappaqua, NY); Forbes; Leonard (Corvallis, OR); Farrar; Paul (South Burlington, VT)
AbstractA method and apparatus for packaging microprocessors and memory devices on a single silicon substrate is described. Microprocessors and memory devices are placed on both sides of the silicon substrate. Through holes are formed in the substrate to connect the microprocessor and memory devices together. By packaging the microprocessor and memory element this way, the propagation length between the memory and the microprocessors is shortened, and timing skews are minimized, and data transmission speed is increased. In addition, additional active and passive circuits and/or components can also be fabricated in one or both sides of the silicon substrate.



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Drawing from US Patent 6424034
High performance packaging for microprocessors and DRAM chips which minimizes timing skews - US Patent 6424034 Drawing
High performance packaging for microprocessors and DRAM chips which minimizes timing skews
Inventor     Ahn; Kie Y. (Chappaqua, NY); Forbes; Leonard (Corvallis, OR); Farrar; Paul (South Burlington, VT)
Owner/Assignee     Micron Technology, Inc. (Boise, ID)
Patent assignment
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Publication Date     July 23, 2002
Application Number     09/144,197
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     August 31, 1998
US Classification     257/723 257/685 257/686 257/777
Int'l Classification     H01L 023/48 H01L 023/52 H01L 029/40
Examiner     Clark; Jhihan B
Assistant Examiner    
Attorney/Law Firm     Dickstein Shapiro Morin & Oshinsky, LLP
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Priority Data    
USPTO Field of Search     257/723 257/777 257/685 257/686 257/698
Patent Tags     high performance packaging microprocessors dram chips which minimizes timing skews
   
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