The invention concerns an arbitration scheme for permitting access to the bus of a computer. The arbitration scheme has the ability to control and reduce the delay experienced by any device by monitoring the queue length of the device and using information concerning the device, such as device rate, phase, data transfer size and queue length. Specifically, the arbiter prevents periodic accessing devices, such as audio and video samplers, from being delayed or interrupted for long periods of time once they have begun accessing the bus.
Disclosed is a bus arbitration system and method which assume that each operation using the bus requires from one to five bus clock cycles. Each potential bus master has a dedicated bus request line and a dedicated bus grant line, both of which are connected to a centralized bus arbiter in the bus arbitration system of the present invention. When a potential bus master wants to use the bus for, for instance, three bus clock cycles, the bus master activates its dedicated bus request line for the same number of bus clock cycles as it would need of bus use (i.e. three bus clock cycles). This three clock wide bus request pulse is recorded in a bus request recording circuit in the centralized bus arbiter. Access to the bus can be granted by the centralized bus arbiter to a winning bus master under any bus arbitration policies. If a potential bus master is chosen to be the winning bus master, the centralized bus arbiter activates the winning bus master's dedicated bus grant line for the same number of bus clock cycles as requested by the bus master, i.e. for three bus clock cycles. So, the bus master will have sufficient use of the bus for its desired operation. After that, the arbiter chooses the next winning bus master and activates its dedicated grant line in the same manner described above, and so on.
A bus controller is provided including a processing means for performing processings of levels having cycle numbers which are different dependent on requesters which respectively issue an access request to a common memory. When it is expected from the present cycle number that a limit cycle number is exceeded, the bus controller selects a processing level with which the processing is performed with a smaller cycle number, or performs a control of giving no permission to a non-realtime bus access request. Thereby, it is possible to design a system with a cycle number that is smaller than the total sum of the maximum access cycle numbers multiplied by the maximum access times over all requesters.
A memory control device for arbitrating memory access contention among bus masters while ensuring, regarding each bus master, the required transfer rate within the required time margin. A device external to LSI 100 writes into the transfer rate information storage unit 111 the transfer rate information indicating the transfer rate and the time period within which the transfer rate is to be ensured. In response, the timing information generator unit 112 determines the shortest time period as a cycle, and also determines, regarding each bus master, time taken to ensure the required transfer rate based on the memory bus bandwidth as a bus use permission time period. The arbiter unit 114 grants the bus use right sequentially with the passage of time to each bus master issuing a bus request for the corresponding bus use permission time period.
