In a shift register for driving a pixel row in a liquid crystal display device a plurality of stages are connected: to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator; to row lines; and in cascade, with respect to a scanning signal, for charging and discharging the row lines. Each stage of the shift register has a pull-up transistor, a pull-down transistor, and first to fourth transistors. The pull-up transistor has a control electrode and a conduction path connected between the first clock signal line and the output terminal. The pull-down transistor has a control electrode and a conduction path connected between the low level voltage line and the output terminal. The first and second transistors have conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor, and each has a control electrode connected commonly to the second clock signal line. The first and second transistors allow a voltage to be charged on the control electrode of the pull-up transistor. The third and fourth transistors have conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor, and each has a control electrode connected commonly to the third clock signal line. The third and fourth transistors allow a voltage to be charged on the control electrode of the pull-down transistor.
A driving circuit for a flat panel display device includes first and second generation units generating m-phase circulation enable control clocks and n-phase circulation form generation clocks; and a plurality of shift register stages generating output signals by using the m-phase circulation enable control clocks and the n-phase circulation form generation clocks. Each shift register stage includes an input terminal receiving the m-phase circulation enable control clocks; first and second nodes outputting first and second signals, respectively, using the m-phase circulation enable control clocks; a first transistor connected to the first node and receiving the n-phase circulation form generation clocks; a second transistor connected to the second node and the first transistor; and an output terminal between the first and second transistors and outputting one of the output signals.
A shift register includes stages shifting an input signal with phase-delayed control signals and first and second supply voltages, and for applying shifted input signals as output signals and as input signals of succeeding stages. Each of the stages includes a first controller selectively applying an input signal and a first supply voltage to a first node between first to third transistors; a second controller selectively applying the first and second supply voltages to a second node between fourth and fifth transistors; and an output buffer selectively applying a predetermined control signal and the first supply voltage as an output signal to a stage output line between sixth and seventh transistors, wherein the fifth transistor may be turned on to sustain a voltage present at the second node equal to the first supply voltage when the fourth transistor is turned off.
When a voltage level of a pulse-cut first clock signal inputted to a first clock terminal is reversed in the state where a first transistor is turned on and a second transistor is turned off, an anti-reversal circuit including a seventh transistor and an eighth transistor supplies a high voltage VDD to a node n2. In this way, a floating state of the node n2 is avoided, and the voltage level of the node n2 is prevented from being reversed. Accordingly, the second transistor will not be turned on in the interval, whereby electric potential of an output signal is stably maintained.
A driver circuit drives display device and LCD device has a driver circuit that includes driving stages and dummy stage. The driving stage includes output and control terminals. The output terminal of the present stage is connected to the control terminal of the previous state to be cascade-connected each other. The driving stage outputs driving signal for controlling the switching device arranged on the display device through the output terminal. The dummy stage includes dummy output terminal and dummy control terminal. The dummy output terminal is connected to the control terminal of the last driving stage to output dummy output signal for turning on or off the last driving stage. The dummy control terminal is connected to the dummy output terminal to be turned on or off by the dummy output signal. The delay of signals is reduced, thereby enhancing display quality.
There is provided a shift register in which multiple stages are connected one after another to each other, the multiple stages having a first stage in which a start signal is coupled to an input terminal, the shift register sequentially outputting output signals of respective stages. The multiple stages have odd stages for receiving a first clock signal, and even stages for receiving a second clock signal having a phase opposite to the first clock signal. Each of the multiple stages has a pull-up section for providing a corresponding one of the first and second clock signals to an output terminal. A pull-up driving section is connected to an input node of the pull-up section, for turning on the pull-up section in response to a front edge of an input signal and for turning off the pull-up section in response to an output signal of a next stage. A pull-down section provides a first power voltage to the output terminal. A pull-down driving section is connected to an input node of the pull-down section, for turning off the pull-down section in response to a front edge of the input signal and turning on the pull-down section in response to the front edge of the output signal of the next stage.
