A low power, low area shift register permits control over delay by dividing the shift register cells into a plurality of segments that are serially connected. A first selector provides data from a shift register input selectively to an input of one of the segments. A second selector provides data from an input or output of a selected cell of one segment of shift register cells to a shift register output.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to U.S. patent application Ser. No. 09/802744, filed concurrently herewith, by inventors Joel W. Page, Wai Laing Lee and Erng Sing Wee, entitled "AN INTEGRATED CIRCUIT ARRANGEMENT FOR MULTIPLE-SENSOR TYPES WITH SELECTABLE FRONT ENDS".
This application is related to U.S. patent application Ser. No. 09/803350, filed concurrently herewith, by inventors Trenton J. Grale and Sijian Chen, entitled "A PROGRAMMABLE TEST MODULATOR FOR SELECTIVELY GENERATING TEST SIGNALS OF DELTA-SIGMA ORDER N".
This application is related to U.S. patent application Ser. No. 09/803349, filed concurrently herewith, by inventors Joel W. Page, Trenton J. Grale, Zhuan Ye, Erng Sing Wee, Sumant Sathe and Sijian Chen entitled "A SIGNAL PROCESSING INTEGRATED CIRCUIT".
