Memory device redundancy selection having test inputs

Claims

What is claimed is:

1. A redundancy match signal latch circuit, comprising:

a pair of reverse-coupled inverters having a first inverter and a second inverter, wherein the first inverter has at least one test input, each for receiving a test input signal;

a latch input for providing a redundancy match signal to the pair of reverse-coupled inverters; and

a latch output for providing a latched match signal from the pair of reverse-coupled inverters;

wherein the first inverter is responsive to one or more control signals to cause the pair of reverse-coupled inverters to generate the latched match signal from either the redundancy match signal or a test input signal;

wherein a logic level of the latched match signal is independent of a logic level of the redundancy match signal when the pair of reverse-coupled inverters generates the latched match signal from a test input signal; and

wherein a logic level of the latched match signal is independent of a logic level of any test input signal when the pair of reverse-coupled inverters generates the latched match signal from the redundancy match signal.

2. The redundancy match signal latch of claim 1, wherein the first inverter is a multiplexer having an inverted first input coupled to receive an output signal of the second inverter.

3. The redundancy match signal latch of claim 1, wherein the first inverter is a multiplexer having an inverted first input coupled to selectively receive an output signal of the second inverter or the redundancy match signal.

4. The redundancy match signal latch of claim 3, wherein the second inverter is a multiplexer having an inverted first input coupled to receive an output signal of the first inverter.

5. A redundancy match signal latch circuit, comprising:

a feedforward inverter having an input for receiving a first signal that is selectively either a redundancy match signal or a feedback signal, and an output for providing an inverted first signal as a feedforward signal; and

a multiplexer having an inverted first input, at least one additional input, and an output for providing the feedback signal, wherein the inverted first input is coupled to receive the feedforward signal and each additional input is coupled to receive a test input signal, further wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs.

6. The redundancy match signal latch of claim 5, wherein the inverted first input of the multiplexer is inverted at a location internal to the multiplexer.

7. The redundancy match signal latch of claim 5, wherein the feedforward inverter is a NAND gate further having a second input for receiving a second signal, and wherein the output of the NAND gate provides the inverted first signal when the second signal has a logic level of logic 1.

8. The redundancy match signal latch of claim 5, wherein at least one of the at least one additional inputs is an inverted input.

9. A redundancy match signal latch circuit, comprising:

a NAND gate having a first input for receiving a first signal, a second input for receiving a second signal that is selectively either a redundancy match signal or a feedback signal, and an output for providing a feedforward signal; and

a multiplexer having an inverted first input, at least one additional input, and an output for providing the feedback signal, wherein the inverted first input is coupled to receive the feedforward signal and each additional input is coupled to receive a test input signal, further wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs.

10. A redundancy match signal latch circuit, comprising:

a NAND gate having a first input for receiving a first signal, a second input for receiving a second signal that is selectively either a redundancy match signal or a feedback signal, and an output for providing a feedforward signal; and

a multiplexer having an inverted first input, at least one additional inverted input, and an output for providing the feedback signal, wherein the inverted first input is coupled to receive the feedforward signal and each additional inverted input is coupled to receive a test input signal, further wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inverted inputs.

11. A redundancy match signal latch circuit, comprising:

a NAND gate having a first input for receiving a first signal, a second input, and an output for providing a feedforward signal;

a multiplexer having an inverted first input, at least one additional input, and an output for providing a feedback signal, wherein the inverted first input is coupled to receive the feedforward signal and each additional input is coupled to receive a test input signal, further wherein the multiplexer is responsive to at least one first control signal to selectively couple its output to either its the first input or one of the at least one additional inverted inputs;

a first selective coupling device having an input coupled to the output of the multiplexer and an output coupled to the second input of the NAND gate; and

a second selective coupling device having an input coupled to receive a redundancy match signal and an output coupled to the output of the first selective coupling device;

wherein the first selective coupling device and the second selective coupling device are each responsive to a second control signal to couple the match signal to, and isolate the feedback signal from, the second input of the NAND gate when the second control signal has a first logic level; and

wherein the first selective coupling device and the second selective coupling device are each responsive to the second control signal to couple the feedback signal to, and isolate the match signal from, the second input of the NAND gate when the second control signal has a second logic level.

12. A redundancy match signal latch circuit, comprising:

a multiplexer having an inverted first input for receiving a first signal that is selectively either a redundancy match signal or a feedback signal, at least one additional input each for receiving a test input signal, and an output for providing a feedforward signal; and

a feedback inverter having an input for receiving the feedforward signal and an output for providing the feedback signal as an inverted feedforward signal;

wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs.

13. The redundancy match signal latch of claim 12, wherein the second input of the multiplexer is also an inverted input.

14. The redundancy match signal latch of claim 12, wherein the inverted first input of the multiplexer is inverted at a location internal to the multiplexer.

15. The redundancy match signal latch of claim 12, wherein the feedback inverter is a NAND gate further having a second input for receiving a second signal, and wherein the output of the NAND gate provides the inverted feedforward signal when the second signal has a logic level of logic 1.

16. A redundancy selection circuit, comprising:

a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:

a pair of reverse-coupled inverters having a first inverter and a second inverter, wherein the first inverter has at least one test input, each for receiving a test input signal;

wherein the first inverter is responsive to one or more control signals to cause the pair of reverse-coupled inverters to generate the latched match signal from either the redundancy match signal or a test input signal;

wherein a logic level of the latched match signal is independent of a logic level of the redundancy match signal when the pair of reverse-coupled inverters generates the latched match signal from a test input signal; and

wherein a logic level of the latched match signal is independent of a logic level of any test input signal when the pair of reverse-coupled inverters generates the latched match signal from the redundancy match signal;

a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant element when the latched match signal has a first logic level and to suppress access to the redundant element when the latched match signal has a second logic level; and

a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary element when the latched match signal has the second logic level and wherein access to the primary element by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

17. A redundancy selection circuit, comprising:

a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:

a feedforward inverter having an input for receiving a first signal that is selectively either the redundancy match signal or a feedback signal, and an output for providing an inverted first signal as a feedforward signal, wherein the latched match signal is derived from the feedforward signal; and

a multiplexer having an inverted first input, at least one additional input, and an output for providing the feedback signal, wherein the inverted first input is coupled to receive the feedforward signal and each additional input is coupled to receive a test input signal, further wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs;

a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant element when the latched match signal has a first logic level and to suppress access to the redundant element when the latched match signal has a second logic level; and

a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary element when the latched match signal has the second logic level and wherein access to the primary element by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

18. A redundancy selection circuit, comprising:

a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:

a NAND gate having a first input for receiving a first signal, a second input for receiving a second signal that is selectively either the redundancy match signal or a feedback signal, and an output for providing a feedforward signal, wherein the latched match signal is derived from the feedforward signal; and

a multiplexer having an inverted first input, at least one additional input, and an output for providing the feedback signal, wherein the inverted first input is coupled to receive the feedforward signal and each additional input is coupled to receive a test input signal, further wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs;

a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant element when the latched match signal has a first logic level and to suppress access to the redundant element when the latched match signal has a second logic level; and

a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary element when the latched match signal has the second logic level and wherein access to the primary element by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

19. A redundancy selection circuit, comprising:

a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:

a multiplexer having an inverted first input for receiving a first signal that is selectively either the redundancy match signal or a feedback signal, at least one additional input each for receiving a test input signal, and an output for providing a feedforward signal, wherein the latched match signal is derived from the feedforward signal; and

a feedback inverter having an input for receiving the feedforward signal and an output for providing the feedback signal as an inverted feedforward signal;

wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs;

a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant element when the latched match signal has a first logic level and to suppress access to the redundant element when the latched match signal has a second logic level; and

a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary element when the latched match signal has the second logic level and wherein access to the primary element by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

20. A memory device, comprising:

a memory array having at least one primary grouping of memory cells and at least one redundant grouping of memory cells; and

addressing circuitry coupled to the memory array for accessing a target memory cell in response to a location address applied to the memory device, wherein the addressing circuitry selectively accesses either a primary grouping of memory cells or a redundant grouping of memory cells in response to a latched match signal from a latch circuit, the latch circuit comprising:

a pair of reverse-coupled inverters having a first inverter and a second inverter, wherein the first inverter has at least one test input, each for receiving a test input signal;

wherein the first inverter is responsive to one or more control signals to cause the pair of reverse-coupled inverters to generate the latched match signal from either a redundancy match signal or a test input signal, the redundancy match signal having a first logic level when the location address matches a known defective address and a second logic level when the location address does not match the known defective address;

wherein a logic level of the latched match signal is independent of the logic level of the redundancy match signal when the pair of reverse-coupled inverters generates the latched match signal from a test input signal; and

wherein a logic level of the latched match signal is independent of a logic level of any test input signal when the pair of reverse-coupled inverters generates the latched match signal from the redundancy match signal.

21. The memory device of claim 20, wherein the primary and redundant groupings of memory cells comprise rows of memory cells.

22. The memory device of claim 20, wherein the memory array is an array of non-volatile memory cells.

23. A memory device, comprising:

a memory array having at least one primary grouping of memory cells and at least one redundant grouping of memory cells; and

addressing circuitry coupled to the memory array for accessing a target memory cell in response to a location address applied to the memory device, wherein the addressing circuitry has a redundancy selection circuit, the redundancy selection circuit comprising:

a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:

a pair of reverse-coupled inverters having a first inverter and a second inverter, wherein the first inverter has at least one test input, each for receiving a test input signal;

wherein the first inverter is responsive to one or more control signals to cause the pair of reverse-coupled inverters to generate the latched match signal from either a redundancy match signal or a test input signal;

wherein a logic level of the latched match signal is independent of the logic level of the redundancy match signal when the pair of reverse-coupled inverters generates the latched match signal from a test input signal; and

wherein a logic level of the latched match signal is independent of a logic level of any test input signal when the pair of reverse-coupled inverters generates the latched match signal from the redundancy match signal;

a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant grouping of memory cells when the latched match signal has a first logic level and to suppress access to the redundant grouping of memory cells when the latched match signal has a second logic level, further wherein the latched match signal has the first logic level when the location address matches a known defective address and has the second logic level when the location address does not match a known defective address; and

a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary grouping of memory cells when the latched match signal has the second logic level and wherein access to the primary grouping of memory cells by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

24. A memory device, comprising:

a memory array having at least one primary grouping of memory cells and at least one redundant grouping of memory cells; and

addressing circuitry coupled to the memory array for accessing a target memory cell in response to a location address applied to the memory device, wherein the addressing circuitry has a redundancy selection circuit, the redundancy selection circuit comprising:

a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:

a feedforward inverter having an input fo