A cache with a translation lookaside buffer (TLB) that reduces the time required for retrieval of a physical address from the TLB when accessing the cache in a system that supports variable page sizing. The TLB includes a content addressable memory (CAM) containing the virtual page numbers corresponding to pages in the cache and a random access memory (RAM) storing the physical page numbers of the pages corresponding to the virtual page numbers in the CAM. The physical page number RAM stores a page mask along with the physical page numbers, and includes local multiplexers which perform virtual address bypassing of the physical page number when the page has been masked.
A system and method for encoding page size information has been described herein. In one embodiment, the method includes determining whether a virtual address is stored in a translation lookaside buffer (TLB), the TLB including a plurality of entries, wherein the entries include a minimum virtual page number bit string and a variable bit string. In one embodiment the method also includes determining whether the first bit string matches the minimum virtual page number bit string of one of the entries. In one embodiment, if the first bit string matches the minimum virtual page number bit string of one of the entries, the method includes decoding a page size stored in the variable portion of the matching entry and a 1-bit field associated with the matching entry, wherein the decoding determines a set of bits of the variable bit string.
Systems and methods are provided for searching at least one content addressable memory entry associated with a content addressable memory (CAM). A given content addressable memory entry comprises a plurality of CAM fields. At least one input selector controls access to the plurality of CAM fields, such that retrieval of a subset of the plurality of CAM fields is selectively enabled. A match evaluator compares an enabled subset of CAM fields to a search value.
