A data rate controller controls a rate that data is transferred over a backplane in a network processing device. A bandwidth allocator allocates bandwidth to an input port for transmitting data over the backplane to an output port. A bandwidth limiter identifies a maximum allowable bandwidth the input port is allocated on the backplane. A bandwidth tracker identifies an amount of bandwidth currently allocated to the input port for transmitting data over the backplane to the output port. When the current allocated bandwidth is used up, the data rate controller prevents that input port from connecting to output ports through the backplane until more bandwidth is allocated.

A technique synchronizes a crossbar switch fabric of a network switch having a plurality of modules configured to transmit and receive data at high speeds. The crossbar switch fabric resides on a switch module and operates on fixed-size cells received at its input ports from line card modules over high-speed serial communication paths of the switch. To eliminate resynchronization between the modules after each serial communications path traversal, each module is allowed to operate within its own clock domain, thereby forcing the entire resynchronization task upon a receive data path of the switch module. Although this results in resynchronization of a "large magnitude", the task only needs to be performed once and entirely on the switch module.

A frame switching apparatus in which it is possible to suppress the operating frequency of the bus and to suppress the cell loss ratio in comparison with that of an ATM cell switching apparatus employing the conventional input buffer system. Since the small capacity buffer Bn-n furnishes a transient storage site for a cell C, a distribution circuit 3.sub.n is able to receive a new cell C.sub.n from the input buffer 2.sub.n to process the received cell. Therefore, head-of-line blocking is less likely to take place. On the other hand, since the small capacity buffer transfers the cell to only one output port, it is sufficient if the switching matrix SWM is of a N:1 multiplexer structure which is far simpler than a complete cross-bandwidth available register structure.

The present invention relates to a method of operating a buffered crossbar switch. The proposed method reduces power dissipation in a buffered crossbar switch by reducing the number of crossbar buffer write processes.

The present invention provides a method and apparatus for arbitration among the inputs of a crossbar cell switch. The input cells of the crossbar cell switch are stored at their respective input ports in input queues prior to switching. The first cell of each input queue is known as the Head of Line (HoL) cell. For each set of HoL cells that may be directed to a specific output port, the HoL cell with the largest input port queue size is assigned to be switched during the current switching epoch. The method and apparatus for arbitration allows the crossbar cell switch to operate with smaller input queues, increasing the throughput of the switch and minimizing both the transit delay for the data cells through the switch and the buffer size needed to accommodate input queues.