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Claims  |
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What is claimed is:
1. A high-speed data transfer synchronizing system, comprising:
a plurality of memory modules for receiving a clock signal to operate in
synchronism with the clock signal, each of said memory modules having at
least one internal clock signal generating circuit to generate at least
one internal clock signal, said at least one internal clock signal
synchronizing with the clock signal, said at least one internal clock
signal generating circuit having a function of adjusting a generation
timing of the internal clock signal having different phases from the clock
signal; and
a memory controller for generating and supplying the clock signal to said
memory modules and transferring/receiving data to/from said memory
modules.
2. A system according to claim 1, wherein said at least one internal clock
signal generating circuit comprises:
a first internal clock signal generating circuit for generating a first
internal clock signal for data write; and
a second internal clock signal generating circuit for generating a second
internal clock signal generating circuit for data read.
3. A system according to claim 2, wherein each of said first and second
internal clock signal generating circuits comprises:
a first buffer circuit for receiving the clock signal;
a first delay circuit having a signal delay time substantially equal to a
signal delay time in said first buffer circuit, said first delay circuit
receiving an output signal from said first buffer circuit and delaying the
output signal from said first buffer circuit;
a second delay circuit for receiving an output signal from said first delay
circuit and delaying the output signal from said first delay circuit by a
predetermined time;
a second buffer circuit for receiving an output signal from said second
delay circuit;
a third delay circuit comprising a plurality of cascaded first delay units
to receive an output signal from said second buffer circuit and delay the
output signal from said second buffer circuit, by transmitting the signal
by said plurality of first delay units, for a period corresponding to a
cycle of the clock signal;
a fourth delay circuit comprising a plurality of cascaded second delay
units to receive the signal delayed by said third delay circuit and delay
the delayed signal by transmitting the signal by the same number of second
delay units as the number of first delay units by which the output signal
from said second buffer circuit is transmitted;
a variable delay circuit for receiving an output signal from said fourth
delay circuit and outputting the output signal from said fourth delay
circuit after delaying the signal by a time corresponding to a control
signal; and
a third buffer circuit having a signal delay time substantially equal to a
signal delay time in said second buffer circuit, said third buffer circuit
receiving an output signal from said variable delay circuit and generating
the internal clock signal.
4. A system according to claim 3, wherein said variable delay circuit
comprises:
a plurality of unit delay elements so connected in series as to have two
terminals and a plurality of series-connected nodes, one of said two
terminals receiving the output signal from said fourth delay circuit; and
a plurality of first switching circuits connected in a one-to-one
correspondence with said series-connected nodes of said unit delay
elements to select signals from said series-connected nodes on the basis
of the control signal.
5. A system according to claim 4, further comprising a second switching
circuit for selecting a signal from a specific one of said
series-connected nodes of said unit delay elements.
6. A system according to claim 3, further comprising a control circuit for
receiving a command from said memory controller and generating the control
signal on the basis of the command.
7. A system according to claim 1, wherein said at least one internal clock
signal generating circuit comprises:
a first pulse delay circuit including a plurality of cascaded first delay
units each having a predetermined signal delay time to transmit a first
pulse by said first delay units;
a second pulse delay circuit including a plurality of cascaded second delay
units each having a predetermined signal delay time to transmit a second
pulse by said second delay units; and
a plurality of state holding circuits formed to have a one-to-one
correspondence with said first delay units in said first pulse delay
circuit and said second delay units in said second pulse delay circuit and
capable of taking reset and set states, a state holding circuit
corresponding to a first delay unit by which the first pulse is
transmitted being set, a second delay unit in said second pulse delay
circuit, which corresponds to said set state holding circuit, transmitting
the second pulse from a second delay unit in a succeeding stage to a
second delay unit in a preceding stage, a second delay unit in said second
pulse delay circuit, which corresponds to a reset state holding circuit,
directly transmitting an internal clock signal to a second delay unit in a
preceding stage, said state holding circuits being divided into a
plurality of groups, and cycles of signals for setting said state holding
circuits in units of groups being sequentially shifted.
8. A system according to claim 7, wherein each of said second delay units
comprises:
a first clocked inverter circuit for receiving an output signal from
another second delay unit as an input signal and operating as an inverter
circuit when receiving an output signal from said state holding circuit
which is in a set state;
a second clocked inverter circuit for receiving said second pulse and
operating as an inverter circuit when receiving an output signal from said
state holding circuit which is in a reset state; and
a NOR gate circuit for receiving output signals from said first and second
clocked inverter circuits.
9. A system according to claim 7, wherein each of said plurality of state
holding circuits comprises:
a signal node for outputting signals corresponding to the set and reset
states;
a first transistor ON/OFF-controlled by an output signal from a second
delay unit in said second pulse delay circuit to supply electric charge to
said signal node; and
a second transistor ON/OFF-controlled by an output signal from a first
delay unit in said first pulse delay circuit to extract electric charge
from said signal node,
a signal corresponding to the set state is obtained at said signal node
when said second transistor is turned on, a signal corresponding to the
reset state is obtained at said signal node when said first transistor is
turned on, and said first and second transistors are so controlled as not
to be turned on at the same time.
10. A system according to claim 7, wherein said plurality of state holding
circuits are divided into two groups, state holding circuits belonging to
each group are alternately arranged to have a one-to-one correspondence
with corresponding first and second delay units in said first and second
pulse delay circuits, and a cycle of the clock signal which nullifies
functions of all said first and second transistors in state holding
circuits belonging to one group and a cycle of the clock signal which
nullifies functions of all said first and second transistors in state
holding circuits belonging to the other group are so controlled as to
alternately appear.
11. A system according to claim 7, wherein said plurality of state holding
circuits are divided into first, second, third, and fourth groups, state
holding circuits belonging to each group are arranged in order and
alternately to have a one-to-one correspondence with corresponding first
and second delay units in said first and second pulse delay circuits, and
a cycle of the clock signal which nullifies functions of all said first
and second transistors in state holding circuits belonging to the first
group, a cycle of the clock signal which nullifies functions of all said
first and second transistors in state holding circuits belonging to the
second group, a cycle of the clock signal which nullifies functions of all
said first and second transistors in state holding circuits belonging to
the third group, and a cycle of the clock signal which nullifies functions
of all said first and second transistors in state holding circuits
belonging to the fourth group are so controlled as to be continuous
cycles.
12. A clock signal generating circuit comprising:
a first buffer circuit for receiving an external clock signal;
a first delay circuit having a signal delay time substantially equal to a
signal delay time in said first buffer circuit, said first delay circuit
receiving an output signal from said first buffer circuit and delaying the
output signal from said first buffer circuit;
a second delay circuit for receiving an output signal from said first delay
circuit and delaying the output signal from said first delay circuit by a
predetermined time;
a second buffer circuit for receiving an output signal from said second
delay circuit;
a third delay circuit including a plurality of cascaded multi-stage first
delay units to receive an output signal from said second buffer circuit
and delay the output signal from said second buffer circuit, by
transmitting the signal by said plurality of first delay units, for a
period corresponding to a cycle of the clock signal;
a fourth delay circuit including a plurality of cascaded multi-stage second
delay units to receive a signal delayed by said third delay circuit and
delay the delayed signal by transmitting the signal by the same number of
second delay units as the number of first delay units by which the output
signal from said second buffer circuit is transmitted;
a variable delay circuit for receiving an output signal from said fourth
delay circuit and outputting the output signal from said fourth delay
circuit after delaying the signal by a time corresponding to a control
signal; and
a third buffer circuit having a signal delay time substantially equal to a
signal delay time in said second buffer circuit, said third buffer circuit
receiving an output signal from said variable delay circuit and generating
an internal clock signal.
13. A circuit according to claim 12, wherein said variable delay circuit
comprises:
a plurality of unit delay elements so connected in series as to have two
terminals and a plurality of series-connected nodes, one of said two
terminals receiving the output signal from said fourth delay circuit; and
a plurality of first switching circuits connected in a one-to-one
correspondence with said series-connected nodes of said unit delay
elements to select signals from said series-connected nodes on the basis
of the control signal.
14. A circuit according to claim 13, further comprising a second switching
circuit for selecting a signal from a specific one of said
series-connected nodes of said unit delay elements.
15. A high-speed data transfer synchronizing method for a high-speed data
transfer synchronizing system comprising:
a plurality of memory modules for receiving a clock signal to operate in
synchronism with the clock signal, each of said memory modules having an
internal clock signal generating circuit to generate at least one internal
clock signal, said at least one internal clock signal synchronizing with
the clock signal, said at least one internal clock signal generating
circuit having a function of adjusting a generation timing of the internal
clock signal on the basis of a control signal; and
a memory controller for generating and supplying the clock signal to said
memory modules and transferring/receiving data to/from said memory
modules, comprising the steps of:
storing a predetermined data pattern in said memory modules;
reading out the data pattern stored in each memory module from said memory
modules and transferring the readout data pattern to said memory
controller; and
comparing the data pattern transferred from each memory module with the
original predetermined data pattern and generating the control signal such
that the two data patterns match.
16. A method according to claim 15, wherein the control signal is generated
on the basis of a command supplied from said memory controller to each of
said memory modules.
17. A method according to claim 15, wherein when the predetermined data
pattern is to be stored in said plurality of memory modules, the data
pattern is transferred from said memory controller at slower transfer
timing than transfer timing in normal operation and stored in said
plurality of memory modules.
18. A method according to claim 15, wherein when the data pattern stored in
each of said plurality of memory modules is to be read out and transferred
to said memory controller, the data pattern is read out as burst data from
each memory module at transfer timing in normal operation.
19. A method according to claim 15, wherein when the predetermined data
pattern is to be stored in said plurality of memory modules, the data
pattern is transferred from said memory controller at transfer timing in
normal operation and stored in said plurality of memory modules, and
when the data pattern stored in each of said plurality of memory modules is
to be read out and transferred to said memory controller, the data pattern
is read out as burst data from each memory module at transfer timing in
normal operation.
20. A high-speed data transfer synchronizing method for a high-speed data
transfer synchronizing system comprising:
a plurality of memory modules for receiving a clock signal to operate in
synchronism with the clock signal, said memory modules previously storing
a predetermined data pattern, each of said memory modules having an
internal clock signal generating circuit to generate at least one internal
clock signal, said at least one internal clock signal synchronizing with
the clock signal, said at least one internal clock signal generating
circuit having a function of adjusting a generation timing of the internal
clock signal on the basis of a control signal; and
a memory controller for generating and supplying the clock signal to said
memory modules and transferring/receiving data to/from said memory
modules, comprising the steps of:
reading out the data pattern previously stored in each memory module and
transferring the readout data pattern to said memory controller; and
comparing the data pattern transferred from each memory module with the
original data pattern previously stored in each memory module and
generating the control signal such that the two data patterns match.
21. A method according to claim 20, wherein the control signal is generated
on the basis of a command supplied from said memory controller to each of
said plurality of memory modules.
22. A method according to claim 20, wherein when the data pattern
previously stored in each of said plurality of memory modules is to be
read out and transferred to said memory controller, the data pattern is
read out as burst data from each memory module at transfer timing in
normal operation. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
The present invention relates to a memory board system including a
plurality of memory modules and a memory controller for controlling these
memory modules to exchange data with the memory modules. The present
invention further relates to a high-speed data transfer synchronizing
system and high-speed data transfer synchronizing method capable of
reliably performing high-speed data transfer in synchronism with a clock
signal even in different device environments constructed of a memory
controller and memory modules.
In the field of information processors, the performance of microprocessor
units (MPUS) has improved, and the capacity of IC memories used has also
greatly increased to 256 Mbits, 1 Gbits, and the like. Under the
circumstances, it is becoming more and more important to efficiently
transfer large amounts of data between a memory module including a
plurality of IC memories and an MPU.
Generally, a memory board system is constructed by combining a plurality of
memory modules and a memory controller.
FIG. 1 shows an outline of the arrangement of a memory board system. A
clock generator CG formed in a memory controller (to be simply referred to
as a controller hereinafter) MEC generates a clock signal. The clock
signal generated by this clock generator CG is sequentially transferred as
a clock signal TCLk along an array of a plurality of memory modules MM1 to
MMn. This clock signal TCLK is returned in the position of the memory
module MMn farthest from the controller MEC. The clock signal TCLK is then
sequentially transferred as a clock signal RCLK in the opposite direction
along the array of the memory modules and transmitted to the controller
MEC. Note that each memory module is formed by, e.g., mounting a plurality
of memory ICs on a print circuit board.
An output command from the controller MEC is transferred to the memory
modules MM1 to MMn via a command bus. Each memory module receives the
command from the command bus in synchronism with the clock signal TCLK and
outputs data to a data bus line in synchronism with the clock signal RCLK.
The readout data output from each memory module to the data bus line is
input to the controller MEC.
Data to be written in each memory module is output from the controller to
the data bus line. Each memory module receives the data from the data bus
line in synchronism with the clock signal TCLK and writes the data in it.
In addition to a clock bus line for transferring the clock signals TCLK
and RCLK, the command bus line for transferring commands, and the data bus
line for transferring data, this memory board system has an address bus
line for transferring address signals. This address bus line is not shown
in FIG. 1.
Each memory module generates two different internal clock signals
synchronizing with the clock signals TCLK and RCLK and controls data read
and write in synchronism with these two internal clock signals. A circuit
for generating such internal clock signals is proposed as a Synchronous
Adjustable Delay (SAD) in U.S. Ser. No. 08/839037 filed by the present
inventor.
In the system shown in FIG. 1, the condition under which data transfer is
normally performed is that the clock signals TCLK and RCLK transferred
through the clock bus line and data transferred through the data bus line
synchronize with each other at any instant. However, this condition is
difficult to completely meet. This is so because it is difficult to
completely equalize the physical conditions, e.g., the resistances and
capacitances of the clock bus line for transferring the clock signals, the
data bus line for transferring data, and the command bus line for
transferring commands.
For this reason, even when one of the memory modules outputs data to the
data bus line in synchronism with the clock signal RCLK, the clock signal
RCLK and the data arrive at the controller with a slight time difference.
This time difference naturally changes in accordance with the position of
a memory module which outputs data. If a cycle time of the clock signal is
much longer than this time difference, the controller can have a
sufficiently long data window, i.e., data input period. So, this time
difference is not a problem.
If the cycle time of the clock signal shortens, however, the time
difference between the clock signal RCLK and data arriving at the
controller is a problem. If this is the case, therefore, the physical
conditions, e.g., the resistances of the clock bus line and the data bus
line must be made as equal as possible to thereby decrease the time
difference and perform high-speed data transfer.
Unfortunately, the degree of freedom of the memory system is lost when the
above method is used. This will be described below with reference to FIGS.
2A and 2B.
FIG. 2A shows the arrangement of a memory board system including one
controller MEC and three memory modules MM1 to MM3. FIG. 2B shows the
arrangement of a memory board system including one controller MEC and four
memory modules MM1 to MM4. The load conditions of the memory modules with
respect to a clock bus line and data bus line are not necessarily the
same. Accordingly, if the physical conditions of the clock bus line and
data bus line are matched in one of the two systems, the conditions in the
other system may differ from the matched conditions.
For example, assume that a signal propagates from the memory module MM3 to
the controller MEC while the bus conditions are matched in the system
shown in FIG. 2B. FIG. 3A shows the relationship between the timings of
the clock signal RCLK and data at the position of the memory module MM3.
in the systems shown in FIGS. 2A and 2B. FIG. 3B shows the relationship
between the timings of the clock signal RCLK and data at the position of
the controller MEC in the systems shown in FIGS. 2A and 2B.
The bus conditions are matched in the system shown in FIG. 2B. Therefore,
in the system shown in FIG. 2B, the clock signal RCLK and data synchronize
with each other at the position of the memory module MM3, as shown in FIG.
3A. In contrast, in the system shown in FIG. 2A, a bus delay time with
respect to the clock signal RCLK is different. Accordingly, as shown in
FIG. 3B, the clock signal RCLK and data do not synchronize with each other
at the position of the controller MEC. For example, if the position of
data moves as indicated by the thick lines in FIG. 3B, the controller can
no longer receive the data at the timing of the leading edge of the
clock,.signal RCLK.
Next, the influence of the characteristics of a bus line on a signal delay
time will be described below. In an ideal case, if a signal line has a
capacitance C and an inductance L per unit length (cm), a signal
propagates the unit length for a time of (C.multidot.L).sup.1/2. In a
general memory board system, if C is 5 to 7 pF and L is 15 to 20 nH, a
signal delay time per unit length is 0.27 to 0.37 nS. Therefore, a
variation in the signal delay time per unit length is (0.37-0.27) nS=0.1
nS. If the length of the whole memory module is 10 cm, a variation in the
signal delay time in the whole memory module is 1 nS. This means that even
if timings in bus lines are optimized in a specific system constructed of
a controller and some memory modules, a signal delay time is shifted about
1 nS in another system having a different number of memory modules.
If a data window, i.e., a data input period equivalent to this time
variation is required, a clock signal cycle of 2 ns, in other words, a
clock signal frequency of 500 MHz is the limit by which data transfer can
be normally performed without strictly equalizing the physical conditions
of bus lines. Note that a command is input in, e.g., every other cycle,
rather than each cycle, with respect to the clock signal TCLK. That is,
the timing of a command can be loosely defined compared to that of data.
So, the same synchronism with the clock signal as that of data is
unnecessary.
As described above, in the conventional memory board system including a
plurality of memory modules and one memory controller, if the cycle of a
clock signal shortens in order to increase the data transfer rate, no
normal operation can be performed any longer depending on the position of
a memory module along a bus line or on the environment of a bus system.
BRIEF SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a
high-speed data transfer synchronizing system and high-speed data transfer
synchronizing method capable of high-speed synchronous data transfer
without very strictly limiting the physical conditions of bus lines
between memory modules and a memory controller.
According to the present invention, there is provided a high-speed data
transfer synchronizing system comprising a plurality of memory modules for
receiving a clock signal to operate in synchronism with the clock signal,
each of the memory modules having at least one internal clock signal
generating circuit to generate at least one internal clock signal
synchronizing with the clock signal from the clock signal and having a
function of adjusting a generation timing of the internal clock signal and
a memory controller for generating and supplying the clock signal to the
memory modules and transferring/receiving data to/from the memory modules.
According to the present invention, there is provided a clock signal
generating circuit comprising a first buffer circuit for receiving an
external clock signal, a first delay circuit having a signal delay time
substantially equal to a signal delay time in the first buffer circuit,
the first delay circuit receiving an output signal from the first buffer
circuit and delaying the output signal from the first buffer circuit, a
second delay circuit for receiving an output signal from the first delay
circuit and delaying the output signal from the first delay circuit by a
predetermined time, a second buffer circuit for receiving an output signal
from the second delay circuit, a third delay circuit comprising a
plurality of cascaded multi-stage first delay units to receive an output
signal from the second buffer circuit and delay the output signal from the
second buffer circuit, by transmitting the signal by the plurality of
first delay units, for a period corresponding to a cycle of the clock
signal, a fourth delay circuit comprising a plurality of cascaded
multi-stage second delay units to receive the signal delayed by the third
delay circuit and delay the delayed signal by transmitting the signal by
the same number of second delay units as the number of first delay units
by which. the output signal from the second buffer circuit is transmitted,
a variable delay circuit for receiving an output signal from the fourth
delay circuit and outputting the output signal from the fourth delay
circuit after delaying the signal by a time corresponding to a control
signal, and a third buffer circuit having a signal delay time
substantially equal to a signal delay time in the second buffer circuit,
the third buffer circuit receiving an output signal from the variable
delay circuit and generating an internal clock signal.
According to the present invention, there is provided a high-speed data
transfer synchronizing method for a high-speed data transfer synchronizing
system comprising a plurality of memory modules for receiving a clock
signal to operate in synchronism with the clock signal, each of the memory
modules having an internal clock signal generating circuit to generate at
least one internal clock signal synchronizing with the clock signal from
the clock signal and having a function of adjusting a generation timing of
the internal clock signal and a memory controller for generating and
supplying the clock signal to the memory modules and
transferring/receiving data to/from the memory modules, and comprising the
steps of storing a predetermined data pattern in the memory modules,
reading out the data pattern stored in each memory module from the memory
modules and transferring the readout data pattern to the memory
controller, and comparing the data pattern transferred from each memory
module with the original predetermined data pattern and generating the
control signal such that the two data patterns match.
According to the present invention, there is provided a high-speed data
transfer synchronizing method for a high-speed data transfer synchronizing
system comprising a plurality of memory modules for receiving a clock
signal to operate in synchronism with the clock signal, each of the memory
modules having an internal clock signal generating circuit to generate at
least one internal clock signal synchronizing with the clock signal from
the clock signal and having a function of adjusting a generation timing of
the internal clock signal and the memory modules previously storing a
predetermined data pattern, a memory controller for generating and
supplying the clock signal to the memory modules and
transferring/receiving data to/from the memory modules, and, comprising
the steps of reading out the data pattern previously stored in each memory
module and transferring the readout data pattern to the memory controller,
and comparing the data pattern transferred from each memory module with
the original data pattern previously stored in each memory module and
generating the control signal such that the two data patterns match.
Additional objects and advantages of the invention will be set forth in the
description which follows, and in part will be obvious from the
description, or may be learned by practice of the invention. The objects
and advantages of the invention may be realized and obtained by means of
the instrumentalities and combinations particularly pointed out
hereinafter.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
The accompanying drawings, which are incorporated in and constitute a part
of the specification, illustrate presently preferred embodiments of the
invention, and together with the general description given above and the
detailed description of the preferred embodiments given below, serve to
explain the principles of the invention.
FIG. 1 is a block diagram showing an outline of the arrangement of a memory
board system;
FIGS. 2A and 2B are block diagrams showing memory board systems having
different arrangements;
FIGS. 3A and 3B are timing charts showing examples of operation timings in
the memory;board systems shown in FIGS. 2A and 2B;
FIG. 4 is a block diagram showing an outline of the arrangement of a memory
board system used to explain the principle of the present invention;
FIGS. 5A and 5B are timing charts of the memory board system shown in FIG.
4;
FIG. 6A is a circuit diagram of a synchronous adjustable delay;
FIG. 6B is a circuit diagram expressing the synchronous adjustable delay
shown in FIG. 6A by using symbols;
FIG. 7 is a block diagram showing the arrangement of a synchronous
adjustable delay different from that shown in FIGS. 6A and 6B;
FIG. 8 is a circuit diagram showing details of the arrangement of a delay
circuit in the synchronous adjustable delay shown in FIG. 7;
FIG. 9 is a timing chart showing an example of an operation of the
synchronous adjustable delay shown in FIG. 7;
FIG. 10 is a circuit diagram showing the arrangement of a synchronous
adjustable delay used in the first embodiment of the present invention;
FIG. 11 is a view showing a practical circuit configuration of a variable
delay circuit in the synchronous adjustable delay shown in FIG. 10;
FIG. 12 is a circuit diagram showing a practical arrangement of a switching
circuit formed in the variable delay circuit shown in FIG. 11;
FIG. 13 is a block diagram showing the configuration of a control signal
generating circuit for generating a control signal used to control the
switching circuit shown in FIG. 12;
FIG. 14 is a circuit diagram showing details of the circuit configuration
of one circuit unit in FIG. 13;
FIG. 15 is a block diagram showing the internal arrangement of a memory
module used in a system according to the first embodiment of the present
invention;
FIG. 16 is a timing chart showing an operation of transferring and storing
4-bit burst data in the first embodiment of the present invention;
FIG. 17 is a flow chart showing an example of control of the operation in
the system of the first embodiment;
FIG. 18 is a flow chart showing an example of control of the operation in
the system of the first embodiment;
FIG. 19 is a schematic block diagram showing a memory board system
according to the second embodiment of the present invention;
FIG. 20 is a timing chart showing the phase relationship between a
plurality of clocks in the second embodiment;
FIG. 21 is a timing chart for explaining a method of forming a timing tM at
which a memory module transfers data without causing any data collisions
in a data bus line without any data transfer gap in the second embodiment;
FIG. 22 is a timing chart showing the relationship between a plurality of
internal clocks in the second embodiment;
FIG. 23 is a timing chart for explaining a practical method of forming the
timing tM by using a synchronous adjustable delay in the second
embodiment;
FIGS. 24A, 24B, and 24C are circuit diagrams showing practical arrangements
of internal clock signal generating circuits for generating various clock
signals shown in FIGS. 22 and 23;
FIG. 25 is a timing chart for explaining the operations of the internal
clock signal generating circuits shown in FIGS. 24A, 24B, and 24C;
FIGS. 26A and 26B are circuit diagrams showing practical circuit
configurations of circuits for generating the internal timing clock
signals shown in FIG. 23;
FIG. 27 is a circuit diagram of a circuit for generating the timing tM in
the second embodiment;
FIG. 28 is a timing chart for explaining a method of generating an internal
timing signal when data is output by using an external clock signal TCLK;
FIGS. 29A and 29B are circuit diagrams showing the configurations of
circuits for generating a clock signal whose phase is shifted 180.degree.
from an internal clock signal synchronizing with the leading edge of a
clock signal;
FIGS. 30A and 30B are circuit diagrams showing internal clock signal
generating circuits by which a variable delay function is given to
internal clock signals Tou, Teu, Rou, and Reu;
FIG. 31 is a timing chart showing the relationship between an external
clock signal and jitters in this external clock signal;
FIG. 32 is a timing chart for explaining the principle of the third
embodiment of the present invention;
FIG. 33 is a block diagram which is a rewrite of the synchronous adjustable
delay shown in FIG. 7;
FIG. 34 is a block diagram showing the arrangement of a synchronous
adjustable delay when jitters contained in an external clock signal are
averaged over two cycles in the third embodiment;
FIGS. 35A and 35B are block diagrams showing the arrangement of a backward
delay when jitters contained in an external clock signal are averaged over
two cycles in the third embodiment;
FIGS. 36A and 36B are block diagrams showing the arrangement of a backward
delay when jitters contained in an external clock signal are averaged over
four cycles in the third embodiment;
FIG. 37 is a view showing a practical circuit configuration of a backward
delay when a small block of the backward delay is constructed of one delay
unit and jitters contained in an external clock signal are averaged over
two cycles in the third embodiment;
FIG. 38 is a view showing a practical circuit configuration of a forward
delay when a small block of the forward delay is constructed of one delay
unit and jitters contained in an external clock signal are averaged over
two cycles in the third embodiment;
FIG. 39 is a circuit diagram showing a state holding circuit and its
control circuit when jitters contained in an external clock signal are
averaged over two cycles in the third embodiment;
FIGS. 40A and 40B are circuit diagrams of a control signal generating
circuit for generating control signals Fo and Fe used in the circuit shown
in FIG. 39;
FIG. 41 is a view showing a practical circuit configuration of a forward
delay when a small block of the forward delay is constructed of one delay
unit and jitters contained in an external clock signal are averaged over
four cycles in the third embodiment;
FIG. 42 is a view showing a practical circuit configuration of a forward
delay when a small block of the forward delay is constructed of one delay
unit and jitters contained in an external clock signal are averaged over
four cycles in the third embodiment;
FIG. 43 is a circuit diagram showing a state holding circuit and its
control circuit when jitters contained in an external clock signal are
averaged over four cycles in the third embodiment; and
FIGS. 44A, 44B, and 44C are circuit diagrams of control signal generating
circuits for generating control signals Fa, Fb, Fc, and Fd used in the
circuit shown in FIG. 43.
DETAILED DESCRIPTION OF THE INVENTION
First, the principle of a high-speed data transfer synchronizing system and
high-speed data transfer synchronizing method according to the present
invention will be described below.
The system of the present invention is a memory board system including one
controller and a plurality of memory modules. To allow synchronous
transfer control of data by using a clock signal having a frequency of,
e.g., 500 MHz or more without strictly restricting the physical conditions
of bus lines, each memory module generates internal clock signals
synchronizing with external clock signals. A predetermined delay time is
added to or subtracted from each internal clock signals, thereby adjusting
the timing of the internal clock signals. By using the internal clock
signals whose timings are adjusted, data read and write timings are
adjusted in each memory module.
With this arrangement, the memory controller is not influenced by the
difference between the timings of data and a clock signal RCLK resulting
from the difference between the numbers of memory modules as shown in FIG.
3B.
This principle of the present invention will be described in more detail
below.
FIG. 4 shows the arrangement of a memory board system, like the memory
board system shown in FIG. 1, which includes one controller MEC and three
memory modules MM1 to MM3 connected through a clock bus line, data bus
line, and command bus line. FIGS. 5A and 5B are timing charts showing some
signals in this memory board system.
If data arriving at the controller delays from the clock signal RCLK as
indicated by the thick lines in FIG. 3B, a memory module for sending data,
e.g., the memory module MM3 is made to output data at a timing (time t1 in
FIG. 5A) earlier than the clock signal RCLK. Also, if the timing at which
data arrives at the controller is early as indicated by the solid lines in
FIG. 3B, a memory module for sending data is made to output data at a
timing (time t2 in FIG. 5B) later than the clock signal RCLK.
As described above, the timing at which a memory module outputs data is
adjusted in accordance with the timing at which data arrives at the
controller. Consequently, data always arrives at the controller in
synchronism with the clock signal RCLK. This realizes reliable high-speed
data transfer between the memory modules and the controller.
In the present invention, the timing adjustment as described above is
performed for each memory module, and this timing adjustment is done by
using the synchronous adjustable delay described previously.
This synchronous adjustable delay described in the specification and views
according to U.S. Ser. No. 08/839037 cited earlier will be described
below.
FIGS. 6A and 6B show the synchronous adjustable delay and an I/O buffer
circuit for inputting and outputting signals with respect to this
synchronous adjustable delay. FIG. 6A expresses the circuit configuration
on a logic gate level. FIG. 6B expresses the circuit configuration by
using symbols. The same reference numerals denote the same parts in FIGS.
6A and 6B.
The synchronous adjustable delay shown in FIGS. 6A and 6B generates an
internal clock signal intRC from an external clock signal RCLK. A
synchronous adjustable delay for generating an internal clock signal intTC
from another external clock signal TCLK has the same arrangement, so a
detailed description thereof will be omitted.
An input buffer circuit 11 having a delay time D1 receives the external
clock signal RCLK. A delay circuit 12 including two buffer circuits
connected in series receives an output signal A from the input buffer
circuit 11 and supplies an output signal to a synchronous adjustable delay
13. This delay circuit 12 has a delay time D (=D1+D2). An output buffer
circuit 14 receives an output signal from the synchronous adjustable delay
13 and generates the internal clock signal intRC. This output buffer
circuit 14 has a delay time D2. Note that the output signal A from the
input buffer circuit 11 is also supplied as a signal B to the synchronous
adjustable delay 13.
The synchronous adjustable delay 13 incorporates two inverter circuits 15
and 16 connected in series, a plurality of cascaded multi-stage delay
units DU1, cascaded multi-stage delay units DU2 equal in number to the
delay units DU1, a NAND gate circuit 21, an inverter circuit 22, a pass
gate circuit 23, NOR gate circuits 24, and NAND gate circuits 25. Each of
the delay units DU1 includes a NAND gate circuit 17 and a NOR gate circuit
18 one input terminal of which receives an output signal from the NAND
gate circuit 17. Each of the delay units DU2 includes a NAND gate circuit
19 and a NOR gate circuit 20 one input terminal of which receives an
output signal from the NAND gate circuit 19. The NAND gate circuit 21
receives an output signal C from the inverter circuit 15 and the output
signal B from the input buffer circuit 11. The inverter circuit 22 inverts
an output signal from the NAND gate circuit 21 and outputs a control
signal S. The pass gate circuit 23 so delays that a delay time from the
input signal B is essentially equal in order to match the timing with the
output signal S from the inverter circuit 22. Each NOR gate circuit 24 and
each NAND gate circuit 25 are inserted between the delay unit DU1 and the
delay unit DU2.
The cascaded multi-stage delay units DU1 construct a forward delay FD.
Likewise, the cascaded multi-stage delay units DU2 construct a backward
delay BD.
The NOR gate circuit 24 and the NAND gate circuit 25 transmit a signal
delayed by the forward delay FD to the backward delay BD at the timing of
the leading edge of the signal B. The NOR gate circuit 24 receives a
control signal /S and an output signal from the NAND gate circuit 17 in
the corresponding delay unit DU1. The NOR gate circuit 24 supplies an
output signal to the NOR gate circuit 20 in the corresponding delay unit
DU2. The NAND gate circuit 25 receives the control signal S and an output
signal from the NOR gate circuit 18 in the corresponding delay unit DU1.
The NAND gate circuit 25 supplies an output signal to the NAND gate
circuit 19 in the corresponding delay unit DU2.
The operation of the synchronous adjustable delay shown in FIGS. 6A and 6B
will be described below. When the external clock signal RCLK rises to HIGH
level, the delay circuit 12 delays this signal by the delay amount D
(=D1+D2). After that, an output signal from the delay circuit 12 is input
to the synchronous adjustable delay 13 and alternately propagates. in the
NAND gates 17 and the NOR gates 18 in the forward delay FD.
The synchronous adjustable delay 13 receives the signal B for setting the
timing at which a pulse signal propagated in the forward delay FD is
transferred to the backward delay BD. A delay amount .DELTA. corresponding
to the time difference between the signal A and the leading edge to HIGH
level of the signal B in the next cycle is detected as the leading edge to
HIGH level of a pulse signal propagating in the forward delay FD (i.e.,
the leading edge to HIGH level of an output signal from the NOR gate
circuit 18 or the trailing edge to LOW level of an output signal from the
NAND gate circuit 17), and the pulse signal is moved to the backward delay
BD. A movement control gate circuit for controlling the movement of this
pulse signal is the circuit constructed of the NOR gate circuit 24 and the
NAND gate circuit 25 inserted between the forward delay FD and the
backward delay BD. Since the signals A and B are identical, a pulse signal
input to the forward delay FD in an immediately preceding cycle is first
moved to the backward delay BD. The NAND gate circuit 21 prevents a pulse
signal input to the forward delay FD in the next cycle from moving to the
backward delay BD after the delay amount D (=D1+D2).
In the synchronous adjustable delay with the above arrangement, the signal
delay amount .DELTA. in each of the forward delay FD and the backward
delay BD changes in accordance with a period T of the external clock
signal RCLK. This signal delay amount .DELTA. is determined by the first
and second pulses of the external clock signal RCLK. The internal clock
signal intRC is formed by using this signal delay amount .DELTA. from the
second pulse. Accordingly, the internal clock signal intRC is in phase
with the external clock signal RCLK from its third pulse.
Letting T be the period of the external clock signal RCLK, D+.DELTA.=T.
Therefore, the internal clock signal intRC is output T after RCLK is
input, and this signal intRC synchronizes with the external clock signal
RCLK.
This synchronous adjustable delay is provided for each memory module
described above. This allows each memory module to generate an internal
clock signal synchronizing with the external clock signal RCLK supplied to
the memory module.
Note that a pulse signal delayed by the forward delay FD can move to the
backward delay BD via the NAND gate circuit 17 or the NOR gate circuit 18
in any position. Accordingly, the accuracy of the timing of the obtained
internal clock signal intRC corresponds to one logic gate circuit.
In this manner, the circuit shown in FIGS. 6A and 6B can generate the
internal clock signal intRC, with substantially no phase difference, in
synchronism with the external clock signal RCLK.
FIG. 7 is a block diagram showing a synchronous adjustable delay having a
different arrangement from that shown in FIGS. 6A and 6B and an I/O buffer
circuit for inputting and outputting signals with respect to this
synchronous adjustable delay. This synchronous adjustable delay also
generates an internal clock signal intRC from an external clock signal
RCLK. A synchronous adjustable delay for generating an internal clock
signal intTC from another external clock signal TCLK has the same
arrangement, so a detailed description thereof will be omitted.
The external clock signal RCLK is input to an input buffer circuit 31
having a delay amount D1. This input buffer circuit 31 outputs a clock
signal CLK having the skew (delay amount) D1 with respect to the external
clock signal RCLK. This clock signal CLK is input to a delay circuit 32
having a delay amount D (=D1+D2). The delay circuit 32 outputs a forward
pulse signal FCL1.
The clock signal CLK and a clock signal /CLK generated by inverting the
clock signal CLK by an inverter circuit 33 are input in parallel to n
delay units 34-1 to 34-n. These n delay units 34-1 to 34-n are cascaded to
form multiple stages. The delay unit 34-1 in the first stage receives the
forward pulse sig | | |
