A solid state image sensor includes an area sensor section having photoelectric conversion pixels arranged in the form of a matrix, a pixel selection section for selecting a pixel of the area sensor section and reading out a video signal, an analog signal processor section for performing signal processing for the video signal, an analog-digital conversion section for converting the processed signal into a digital signal, a digital signal processor section for performing signal processing to convert the digital signal into a digital signal having a predetermined signal format, and an interface section which operates in accordance with an external command, and has the function of selecting a video signal obtained by digitizing a pixel or a signal obtained by performing processing for the luminance and color difference signals of the video signal. These sections are mounted on a single chip.
A photoelectric conversion device formed on a single semiconductor substrate, including: a plurality of photoelectric conversion elements; a read-out circuit including a switch for reading out analog signals from the photoelectric conversion elements; a buffer circuit for driving the switch; and a logic circuit for processing digital signals. A first semiconductor area to which a ground level for the buffer circuit is supplied and a second semiconductor area to which a ground level for the logic circuit is supplied are electrically separated from each other.
In an image reader, delay circuits are disposed on connection lines connecting an A/D converter with an image data generation circuit, whereby the output timings of the digital electric signals output from the A/D converter differ. Thus, the digital electric signals are not output at the same time from the adjacent output terminals of the A/D converter. Thus, the digital electric signals output from the A/D converter do not make a low to high or high to low transition at the same time and amplifying of EMI is decreased. Therefore, noise can be prevented from being contained in image data generated by the image data generation circuit and the quality of the image read through the image reader can be improved.
The invention provides an image processing apparatus wherein, when an image of an imaging object is picked up and converted into image data and the image data is compressed, the data amount can be reduced without deteriorating the picture quality. The image processing apparatus includes an image pickup section for picking up an image of an imaging object and converting the image into image data, a compression section for compressing the image data and outputting the compressed data, a detection section for detecting a data amount of the compressed data, and a control section for controlling an optical condition for the image picked up by the image pickup section in response to the data amount of the compressed data detected by the detection section. The compression section compresses the image data obtained by the conversion of the image pickup section based on the optical condition controlled by the control section.
A solid-state image sensor includes a photocell array for accumulating signal charge for each pixel in accordance with progress of exposure, and a read circuit for reading out information on the accumulated signal charge from the photocell array. With an insulating structure between its input and output, an amplifier in the read circuit generates an output signal without resetting the accumulated charge in the photocell. Information on the accumulated charge is read out at different exposure times while signal charge is accumulated during exposure, and a plurality of image signals can sequentially be obtained without destroying the information.
A photoelectric conversion device formed on a single semiconductor substrate, including: a plurality of photoelectric conversion elements; a read-out circuit including a switch for reading out analog signals from the photoelectric conversion elements; a buffer circuit for driving the switch; and a logic circuit for processing digital signals. A first semiconductor area to which a ground level for the buffer circuit is supplied and a second semiconductor area to which a ground level for the logic circuit is supplied are electrically separated from each other.