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Voltage level translator systems and methods
   
Document Number
US Patent 6462602
Issued Date
October 8, 2002
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Abstract
A voltage level translator is provided that operates over a wide range of voltage levels at a fast translation speed. The voltage level translator includes an input terminal that receives an input signal and a capacitor having its first terminal coupled to the input terminal. A clamp circuit is coupled to the input terminal and to the second terminal of the capacitor and operable to provide a signal on the second terminal of the capacitor in response to a first voltage level of the input signal. A voltage source circuit is coupled to the clamp circuit and to the second terminal of the capacitor and provides a signal on the second terminal of the capacitor in response to a second voltage level of the input signal. An output buffer has a first input terminal coupled to the first terminal of the capacitor and a second input terminal coupled to the second terminal of the capacitor. The output buffer provides an output signal having a translated voltage level on its output terminal in response to signals on the first and second terminals of the capacitor.
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Number of Claims:
23
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Owner
Published
October 8, 2002
Application Number
09/775,488
Filed
February 1, 2001
US Classification
327/333   327/112 327/390
Int'l Classification
H03K   19/0185   (20060101)  
Assistant Examiner
USPTO Field of Search
327/390   327/333   327/589   327/112   326/63   326/68   326/80   326/81  
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