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Claims  |
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What is claimed is:
1. A semiconductor integrated circuit device comprising:
memory mats arranged in a first direction,
each of said memory mats including memory cells arranged in said first
direction and a second direction, perpendicular to said first direction,
said memory cells being formed in a well region, formed in a substrate,
respectively;
first power supply lines electrically connected to said memory cells and
extending on said memory mats in said first direction; and
second power supply lines and third power supply lines extending over said
first power supply lines in said second direction and arranged between
adjacent ones of said memory mats, in said first direction,
said second power supply lines being electrically connected to said first
power supply lines, and
said third power supply lines being electrically connected to said well
region.
2. A semiconductor integrated circuit device according to claim 1,
wherein said second power supply lines and said third power supply lines
extend over a word shunt area, and
wherein at said word shunt area said third power supply lines are
electrically connected to said well region.
3. A semiconductor integrated circuit device according to claim 1, wherein
switch circuits are placed at both of opposing ends of said memory mats,
in said second direction, and are, respectively, electrically connected to
corresponding ones of said third power supply lines through a transistor
for supplying one of a first voltage and a second voltage, lower than said
first voltage.
4. A semiconductor integrated circuit device according to claim 1, wherein
ones of said second power supply lines are electrically connected to
corresponding ones of said third power supply lines at outside said memory
mats.
5. A semiconductor integrated circuit device comprising:
memory mats arranged in a first direction,
each of said memory mats including memory cells arranged in said first
direction and a second direction, perpendicular to said first direction,
said memory cells being formed in a well region, formed in a substrate,
respectively;
power supply lines extending in said second direction and arranged between
adjacent ones of said memory mats in said first direction,
said power supply lines being electrically connected to said well region;
and
switch circuits placed at both of opposing ends of said memory mats, in
said second direction, and are, respectively, electrically connected to
corresponding ones of said power supply lines through a transistor for
supplying one of a first voltage and a second voltage, lower than said
first voltage.
6. A semiconductor integrated circuit device according to claim 5, further
comprising:
sense amplifying circuits each of which is arranged in said second
direction between a corresponding one of said memory mats and a
corresponding one of said switch circuits.
7. A semiconductor integrated circuit device according to claim 5,
wherein each of said power supply lines extends over a word shunt area, and
wherein at said word shunt area each of said power supply lines is
electrically connected to said well region.
8. A semiconductor integrated circuit device according to claim 5, wherein
said power supply lines are electrically connected to memory cell supply
lines at outside said memory mats, said memory cell supply lines extend
over said memory cells in said first direction.
9. A semiconductor integrated circuit device comprising:
memory mats arranged in a first direction,
each of said memory mats including memory cells arranged in said first
direction and a second direction, perpendicular to said first direction,
said memory cells being formed in a well region, formed in a substrate,
respectively;
first power supply lines electrically connected to said memory cells; and
second power supply lines and third power supply lines formed over said
first power supply lines, extending in said second direction, and arranged
between said adjacent memory mats in said first direction,
said second power supply lines being electrically connected to said first
power supply lines, and
said third power supply lines being electrically connected to said well
region.
10. A semiconductor integrated circuit device according to claim 9,
wherein said second power supply lines and said third power supply lines
extend over a word shunt area, and
wherein at said word shunt area said third power supply lines are
electrically connected to said well region.
11. A semiconductor integrated circuit device according to claim 9, wherein
switch circuits are placed at both of opposing ends of said memory mats,
in said second direction, and are, respectively, electrically connected to
corresponding ones of said third power supply lines through a transistor
for supplying one of a first voltage and a second voltage, lower than said
first voltage.
12. A semiconductor integrated circuit device according to claim 9, wherein
ones of said second power supply lines are electrically connected to
corresponding ones of said third power supply lines at outside said memory
mats.
13. A semiconductor integrated circuit device comprising:
a first memory array and a second memory array arranged in a first
direction,
each of the memory arrays including memory cells arranged in said first
direction and in a second direction, perpendicular to said first
direction,
said memory cells being formed in a well region, formed in a substrate,
respectively;
a first power supply line electrically connected to said memory cells; and
a second power supply line and a third power supply line formed over said
first power supply line, extending in said second direction, and arranged
between said first memory array and said second memory array in said first
direction,
said second power supply line being electrically connected to said first
power supply line, and
said third power supply line being electrically connected to said well
region.
14. A semiconductor integrated circuit device according to claim 13,
wherein said second power supply line and said third power supply line
extend over a word shunt area, and
wherein at said word shunt area said third power supply line is
electrically connected to said well region.
15. A semiconductor integrated circuit device according to claim 13,
wherein switch circuits are placed at both of opposing ends of said first
and second memory arrays, in said second direction, near said second and
third power supply lines, and are electrically connected to said third
power supply line through a transistor for supplying one of a first
voltage and a second voltage, lower than said first voltage.
16. A semiconductor integrated circuit device according to claim 13,
wherein said second power supply line is electrically connected to said
third power supply line at outside said first and second memory mats.
17. A semiconductor integrated circuit device comprising:
memory mats arranged in a first direction,
each of said memory mats including memory cells arranged in said first
direction and a second direction, perpendicular to said first direction,
said memory cells being formed in a well region, formed in a substrate,
respectively;
first power supply lines electrically connected to said memory cells and
extending on said memory mats in said first direction; and
second power supply lines and third power supply lines extending over said
first power supply lines in said second direction and arranged between
adjacent ones of said memory mats in said first direction,
said second power supply lines being electrically connected to said first
power supply lines,
said third power supply lines being electrically connected to said well
region, and
said second power supply lines being electrically connected to said third
power supply lines at outside said memory mats.
18. A semiconductor integrated circuit device according to claim 17,
wherein said second power supply lines and said third power supply lines
extend over a word shunt area, and
wherein at said word shunt area said third power supply lines are
electrically connected to said well region.
19. A semiconductor integrated circuit device according to claim 17,
wherein switch circuits are placed at both of opposing ends of said memory
mats, in said second direction, near said second and third power supply
lines, and are electrically connected to corresponding ones of said third
power supply lines through a transistor, and
wherein said second power supply lines are electrically connected to said
third power supply lines at outside said switch circuits.
20. A semiconductor integrated circuit device according to claim 1,
wherein said first direction corresponds to a data line direction and said
second direction corresponds to a word line direction of said memory mats,
respectively, and
wherein each of said memory cells in at least one of said memory mats is a
static random access memory cell including a cross-coupled CMOS latch
circuit and a pair of transfer MISFETs which are coupled between
input/output nodes of said latch circuit and a corresponding pair of
complementary data lines, respectively.
21. A semiconductor integrated circuit device according to claim 20,
wherein each word line is associated with a row of memory cells, each said
row of memory cells in at least one of said memory mats is disposed such
that in each memory cell N-channel MISFETs are provided in a p well region
and p-channel MISFETs are provided in an n well region, the n well region
and p well region associated with each memory cell in a row are disposed
in parallel, and the n well regions and the p well regions of each said
row are, respectively, disposed as an integrally formed N-well and an
integrally formed P-well, both extended in said first direction.
22. A semiconductor integrated circuit device according to claim 21,
wherein said N-well and said P-well associated with each row of memory
cells, combinedly, overlie a similarly directioned buried well region,
having one of a p and n-type conductivity, formed in said substrate,
having the other of the p and n-type conductivity.
23. A semiconductor integrated circuit device according to claim 1, wherein
said second and third power supply lines are disposed as plural sets each
including a pair of adjacently disposed power supply lines and a pair of
substrate potential supply lines, separated by said pair of power supply
lines, and each set being disposed in a spacing between each adjacent pair
of memory mats.
24. A semiconductor integrated circuit device according to claim 23,
wherein each said spacing where a set of power supply and substrate
potential supply lines are disposed constitutes a word shunt area of the
device.
25. A semiconductor integrated circuit device according to claim 24,
wherein said second and third power supply lines are formed at a same
level, metal conductive layer.
26. A semiconductor integrated circuit device according to claim 25,
wherein said first power supply lines are formed from a lower level
conductive layer than that of said second and third power supply lines. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
This invention relates to a method of designing a semiconductor integrated
circuit device, and a technique effective in a case in which a plurality
of circuits different in characteristic from each other are prepared as a
cell library and a user selects a desired circuit from the cell library in
the course of design of a semiconductor integrated circuit device. This
invention also relates to a technique which is effective for use in the
design of an ASIC (Application Specific Integrated Circuit), for example.
It has been known that a semiconductor logic integrated circuit device
principally using field effect transistors like MOSFETs
(Metal-Oxide-Semiconductor Field Effect Transistors) is capable of
operating at high speed as the threshold voltage of each MOSFET decreases;
whereas, since a substantial leakage current is produced during its off
state when the threshold voltage thereof is low, the use of a
semiconductor logic integrated circuit device will lead to an increase in
power consumption. As a characteristic of each MOSFET, a so-called
substrate bias effect is known, wherein the threshold voltage thereof will
go high as a reverse bias voltage between the source thereof and a base
(substrate or well region) increases. Further, a technique for controlling
a standby current has been described in Japanese Published Unexamined
Patent Application No. Hei 7-235608, for example.
SUMMARY OF THE INVENTION
A technique, wherein an inverter circuit or an inverter INV, capable of
switching the potentials of bases (n well and p well) to a source voltage
Vcc and a reference voltage Vss, and base or substrate bias voltages Vbp
(Vbp>Vcc) and Vbn (Vbn>Vcc), as shown in FIGS. 21(A) and 21(B), is
used in place of an inverter INV wherein the potentials of bases (n well
and p well) shown in FIGS. 20(A) and 20(B) are fixed to a source voltage
Vcc and a reference voltage Vss (Vcc>Vss), respectively, has been
described in, for example, "ISSCC Dig. of Tech. Papers", pp. 166-167, 437,
February 1996, or IEEE CICC, pp. 53-56, May 1996.
According to this technique, the source voltages Vcc and Vss are applied to
the bases (n well and p well) when the circuit is in operation (active),
to thereby supply a low reverse bias voltage between the source and
substrate or base, whereby each MOSFET is set to a low threshold so as to
operate the circuit device at high speed. On the other hand, when the
circuit is deactivated (at standby), the substrate bias voltages Vbp and
Vbn are applied to the bases (n well and p well) to supply a high reverse
bias voltage between the source and the base (well), thereby increasing
the threshold of each MOSFET to reduce the leakage current, whereby low
power consumption is provided. The present inventors have discussed the
semiconductor integrated circuit device using MOSFETs capable of
performing switching to the substrate bias voltages. As a result, it
became evident that the following problems were inherent in such a device.
When the threshold of each MOSFET is controlled using the above described
substrate bias effect in an attempt to realize an IC having desired
characteristics, an inconvenience occurs in that wiring or wires for
supplying the bias voltages to the well regions used as the bases of the
respective MOSFETs are required in large numbers (Vcc line, Vbp/Vcc line,
Vss line and Vbn/Vss line) and the area occupied by the circuit, and, in
turn, the chip size of the IC, increases.
The development of an ASIC or the like will call for consideration of two
cases: a first case where a user desires an IC having low power
consumption or reduced chip size even if its operating speed is slow; and
a second case where the user desires an IC capable of operating at high
speed even if the power consumption increases more or less. When the
reverse bias voltage between the source and base (well) is increased or
decreased in an attempt to realize the above-described ICs which are
different in characteristic from each other, a maker must separately
design substrate potential fixed circuit cells and substrate potential
variable circuit cells suitable for the respective ICs and prepare them as
separate cell libraries. Therefore, the design effort increases, and the
labor, such as the extraction of characteristics including delay times or
the like of the circuit cells, required when the user designs and
evaluates the chip using these circuit cells, the description thereof in
the specifications (data sheet or data book), etc. also increases, i.e.,
the burden of preparing respective specifications for corresponding cell
libraries increases.
An object of the present invention is to provide a design technique capable
of implementing ICs which are different in cell type from each other
without having to increase the burden on the designer.
Another object of the present invention is to provide a design technique
capable of easily implementing a semiconductor integrated circuit device
in which its chip size, power consumption and operating speed are
optimized.
The above, other objects and novel features of this invention will become
apparent from the description provided by the present specification and
the accompanying drawings.
A summary of a typical one of the features disclosed in the present
application will be described as follows:
Design information about circuit cells each having a desired function are
described as objects according to desired purposes and are registered in a
cell library registered with a plurality of circuit cells for forming ASIC
or the like as design resources in the form of cell information capable of
forming any of substrate potential fixed and variable cells by only the
deletion or addition of information about predetermined objects.
Incidentally, the present cell library is stored in a storage medium such
as a magnetic disc, an optical disk, a printed material or the like.
As a typical one of the above-described circuit cells, a cell is known
which comprises a pair consisting of a p channel MOSFET and an n channel
MOSFET constituting a CMOS inverter which falls under the designation of a
minimum unit in a circuit, for example. Others used as the circuit cells
registered in the cell library may include a basic circuit cell, such as a
flip-flop, a NOR gate, a NAND gate or the like, as frequently used in a
logic LSI, a CPU peripheral circuit module, such as a CPU core used as a
control circuit, a random access memory used as a memory circuit, a timer,
a serial communication interface circuit or the like, and a macrocell like
an A/D converter, a D/A converter or the like used as a signal processing
circuit.
According to the above feature, since only one kind of cell may be designed
for circuits having the same function, a maker can reduce the burden on
the design and labor, such as the extraction of characteristics such as
voltage dependency, temperature dependency, delay times or the like of
each designed cell, the description thereof in the specifications, etc.,
and, in its turn, achieve a reduction in cost as well.
Further, a semiconductor integrated circuit device wherein the chip size,
power consumption and operating speed are optimized, can easily be
implemented by properly using substrate potential fixed and variable cells
according to the functions or the like of circuit portions used with cells
on one semiconductor chip and mixing them together in this condition.
Typical ones of various features of the present invention have been
described in brief. However, the various embodiments of the present
invention and specific configurations of these embodiments will be more
fully set forth in the following description.
BRIEF DESCRIPTION OF THE DRAWINGS
While the specification concludes with claims particularly pointing out and
distinctly claiming the subject matter which is regarded as the invention,
it is believed that the invention, the objects and features of the
invention and further objects, features and advantages thereof will be
better understood from the following description taken in connection with
the accompanying drawings in which:
FIG. 1 is a plan view showing one example of the layout pattern a common
cell topology for a CMOS inverter to which the present invention is
applied;
FIG. 2 is a cross-sectional view illustrating an example of a section taken
along line II--II of FIG. 1;
FIG. 3(A) is a plan view of a layout pattern showing an object A;
FIG. 3(B) is a plan view of a layout pattern depicting an object B;
FIG. 3(C) is a plan view of an object CP;
FIG. 3(D) is a plan view of an object CN;
FIG. 3(E) is a plan view of an object DWL;
FIG. 3(F) is a plan view of an object DTH;
FIG. 3(G) is a plan view of an object E;
FIG. 3(H) is a plan view of an object F;
FIG. 3(I) is a plan view of an object G;
FIG. 3(J) is a plan view of an object H;
FIGS. 4(A) and 4(B) are, respectively, plan views showing layout patterns
of a substrate potential fixed CMOS inverter and a substrate potential
variable CMOS inverter each constructed using a common cell topology for a
CMOS inverter;
FIG. 5(A) is a circuit diagram illustrating an example of a configuration
of a substrate bias control circuit using substrate potential variable
CMOS inverter cells;
FIG. 5(B) is a plan view showing a layout pattern of substrate potential
variable logic cells;
FIG. 5(C) is a plan view illustrating a layout pattern of substrate
potential fixed logic cells;
FIG. 6(A) is a circuit diagram depicting another example of a substrate
bias control circuit using substrate potential variable CMOS inverter
cells;
FIG. 6(B) is a plan view showing a layout pattern of a substrate potential
fixed logic cell row;
FIG. 7(A) is a plan view of a layout pattern illustrating another example
of a common cell topology for a CMOS inverter;
FIG. 7(B) is a plan view of a layout pattern depicting an object B';
FIG. 8(A) is a plan view showing one example of a memory array to which the
present invention is applied;
FIG. 8(B) is a plan view of a detail of FIG. 8(A);
FIG. 9 is a plan view illustrating a memory mat having memory cell power
supply portions to which the present invention is applied;
FIG. 10(A) is a plan layout pattern view and
FIGS. 10(B) and 10(C) are cross-sectional views showing an embodiment of a
common cell topology for a memory cell power supply portion;
FIG. 11(A) through FIG. 11(D) are respective plan views illustrating the
layout pattern of an example of each object configuration of a memory cell
power supply portion;
FIG. 12(A) through FIG. 12(C) are respective plan views depicting the
layout pattern of an embodiment of a cell topology of each memory cell;
FIG. 13 is a circuit diagram showing one embodiment of a memory cell;
FIG. 14 is a flowchart for describing a procedure for creating a library
registered with cells;
FIG. 15 is a diagram showing a portion of an inverter cell part prepared in
Step ST3 of the flowchart shown in FIG. 14;
FIG. 16 is a block diagram showing an example of an ASIC configuration used
as one example of a semiconductor integrated circuit device constructed
using a common cell topology according to the present invention;
FIG. 17 is a block diagram illustrating another embodiment of an LSI which
can be designed using a common cell topology according to the present
invention;
FIG. 18(A) to FIG. 18(C) are conceptual diagrams showing modifications of
an LSI to which the present invention is applied.
FIG. 19(A) is a cross-sectional view showing a structure of an LSI having a
well-separate configuration, which is used as another embodiment of the
present invention, and
FIGS. 19(B) and 19(C) are respective plan views showing an example of each
object configuration;
FIG. 20(A) is a circuit diagram illustrating an equivalent circuit of a
substrate potential fixed CMOS inverter;
FIG. 20(B) is a cross-sectional view depicting a structure of the circuit
shown in FIG. 20(A);
FIG. 21(A) is a circuit diagram illustrating an equivalent circuit of a
substrate potential variable CMOS inverter; and
FIG. 21(B) is a cross-sectional view showing a structure of the circuit
shown in FIG. 21(A).
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Preferred embodiments of the present invention will hereinafter be
described with reference to the accompanying drawings.
A description will first be made of how to view common cell topology, using
a CMOS (Complementary MOS) inverter cell INV as an illustrative example.
FIGS. 1 and 2 respectively show one example of a common cell topology for a
CMOS inverter cell INV comprised of a pair of elements including a p
channel MISFET (Metal Insulator Semiconductor FET) Qp and an n channel
MISFET Qn. Of these, FIG. 1 illustrates an example of a layout pattern of
a circuit cell and FIG. 2 shows an example of a sectional view taken along
line II--II of FIG. 1.
In FIGS. 1 and 2, reference numeral 100 indicates a p-type single-crystal
silicon substrate used as a base, for example. Reference numeral 100i
indicates a device or element separator, and reference numerals 101 and
102 indicate an n well region (101a, 101b) and a p well region (102a,
102b) defined as relatively low-density n-type and p-type semiconductor
regions provided side by side in contact with each other, respectively.
Reference numerals 103 and 104 respectively indicate a Vcc line and a Vss
line used as power wired layers, which are respectively provided along the
upper and lower sides of the n well region 101 and p well region 102.
Reference numerals 105 and 106 respectively indicate a VBP line and a VBN
line used as substrate potential supply wired layers located on the
further outer sides of the Vcc line 103 and Vss line 104 and arranged in
parallel to these wired layers. These power supply lines (103 through 106)
are made up of a metal (aluminum) layer corresponding to a first layer,
for example. Further, the power supply lines (103 through 106) are
constructed so as to extend in a cell row direction.
Reference numeral 107 indicates an active region in which the p channel
MISFET Qp is formed. Reference numeral 108 indicates an active region in
which the n channel MISFET Qn is formed. The active regions 107 and 108
are defined by the device separator 100i. Reference numerals 107a and 107b
respectively indicate relatively low-density p-type semiconductor regions
and relatively high-density p+type semiconductor regions provided in the n
well region 101 and the active region 107. They serve as a source-to-drain
region of the p channel MISFET Qp. Reference numerals 108a and 108b
respectively indicate relatively low-density n-type semiconductor regions
and relatively high-density n+type semiconductor regions provided in the p
well region 102 and the active region 108. They serve as a source-to-drain
region of the n channel MISFET Qn. Reference numeral 109 indicates a gate
electrode comprised of a polysilicon film or the like, which is provided
so as to extend in the direction normal to the power supply lines 103 and
104 across the p well region 101 and the n well region 102. The gate
electrode 109 is formed integrally with a gate electrode 109p of the p
channel MISFET Qp and a gate electrode 109n of the n channel MISFET Qn.
The gate electrodes 109n and 109p are respectively formed on the well
regions 101 and 102 with gate insulating films 109i interposed
therebeween. Further, a channel forming region of the p channel MISFET Qp
is formed integrally with the n well region 101, whereas a channel forming
region of the n channel MISFET Qn is formed integrally with the p well
region 102.
Further, reference numeral 110 indicates a common drain electrode comprised
of, for example, the metal (aluminum) layer or the like corresponding to
the first layer, which is disposed in the direction orthogonal to the
power supply lines 103 and 104 across the n well region 101 and the p well
region 102. The common drain electrode 110 is designed so as to be
electrically connected via contact holes CH1 and CH2 to the p-type
semiconductor regions 107a and 107b and n-type semiconductor regions 108a
and 108b respectively used as the source-to-drain regions at both ends.
Incidentally, symbols CH3 indicate contact holes for electrically
connecting the Vcc line 103 to the n well region 101, symbols CH4 indicate
contact holes for electrically connecting the Vss line 104 to the well
region 102, symbols CH5 indicate contact holes for respectively
electrically connecting the VBP line 105 to the n well region 101, symbols
CH6 indicate contact holes for respectively electrically connecting the
VBN line 106 to the p well region 102, symbol CH7 indicates a contact hole
for electrically connecting the Vcc line 103 to the p-type semiconductor
regions 107a and 107b serving as the source-to-drain region of the p
channel MISFET Qp, and symbol CH8 indicates a contact hole for
electrically connecting the Vss line 104 to the n-type semiconductor
regions 108a and 108b serving as the source-to-drain region of the n
channel MISFET Qn. Further, contact regions 111 through 114 comprised of
high-density semiconductor regions for reducing contact resistance are
respectively provided at substrate surface positions corresponding to the
contact holes CH3 through CH6 of these contact holes, for supplying
potentials to the well regions.
Incidentally, the contact regions 111 and 113 indicate n+type semiconductor
regions, which are formed in the same process as that for the
semiconductor region 108b, for example. The contact regions 111 through
114 and the active regions 107 and 108 are defined by the device separator
100i. The device separator 100i is formed by a structure in which an
insulating film is embedded in a groove defined in the base 100.
Referring to FIGS. 1 and 2, symbol TH1 indicates a through hole used as an
input terminal for electrically connecting the gate electrode 109 to a
metal layer (upper wire or interconnection) 110' used as a first layer,
which is located above the gate electrode 109 and is made up of an
aluminum layer or the like. Symbol TH2 indicates a through hole used as an
output terminal for electrically connecting the drain electrode 110 to a
metal layer (upper interconnection) 110" used as a first layer, which is
located above the drain electrode 110 and is comprised of an aluminum
layer or the like. CH1 through CH9 and TH1 are formed at the same height.
In FIG. 2, conductive layers 120 formed over the surfaces of the
source-to-drain regions 107a and 107b and 108a and 108b and the contact
regions 111 through 114 are formed of a metal silicide layer (CoSi, TiSi
or the like) for providing low resistance as well as on the surface of the
polysilicon gate electrode 109. The conductive layers 120 and the power
supply lines 103 through 106 are respectively spaced away from one another
by an interlayer insulating film 121 and are respectively electrically
connected to one another by connecting bodies 122 comprised of a
conductive material such as tungsten or the like charged into the contact
holes CH1, CH2, CH3, CH4 and CH5 through CH8 defined in the interlayer
insulating film 121.
In the present embodiment, design data constituting the CMOS inverter INV
is divided into the following objects A, B, CP, CN, DWL, DTH, E, F, G and
H. That is, the VBP line 105 and VBN line 106, the contact holes CH5, CH6,
contact regions 113 and 114 for respectively connecting these to the n
well region 101 and p well region 102, and the n well 101a and p well 102a
corresponding to parts of the well regions 101 and 102 just below or under
the VBP line 105 and VBN line 106, respectively, constitute design data.
These design data are prepared as one united object A (see FIG. 3(A).
Similarly, the contact holes CH3 and CH4 and contact regions 111 and 112
for electrically connecting the Vcc line 103 and the Vss line 104 to the n
well region 101 and p well region 102, and protrusions 103a and 104a used
for providing contact with the Vcc line 103 and the Vss line 104,
respectively, constitute design data. These design data are prepared as
one united object B (see FIG. 3(B).
The active region 107, p-type semiconductor regions 107a and 107b and gate
electrode 109p constitute design data as the p channel MISFET Qp which
constitutes the inverter cell. These design data are prepared as one
united object CP (see FIG. 3(C). The active region 108, n-type
semiconductor regions 108a and 108b and gate electrode 109n make up design
data as the n channel MISFET Qn which constitutes the inverter cell. These
design data are prepared as one unified object CN (see FIG. 3(D).
As shown in FIGS. 3(C) through 3(J), other objects are also similarly
configured as a unit of design data. That is, there are known, as other
objects, an output contact structure (object DTH) comprising the drain
electrode 110 (object DW) of the metal layer used as the first layer, and
the through hole TH2 for connecting the drain electrode 110 to a wired
layer (signal line) defined as an upper layer; an input contact structure
(object E) comprising the through hole TH1 for connecting each gate
electrode to an upper wired layer (signal line), and a buffer conductive
layer BFM; a contact structure (object F) comprising the contact holes
CH1, CH2, CH7 and CH8 for connecting the conductive layers such as the
power supply lines 103 and 104, the drain electrode 110, etc. to the
diffusion layers 107a, 107b, 108a and 108b, and high-density contact
regions 107' and 108'; and a well structure (object H) for providing a
conductive layer pattern (object G) constituting the power supply lines
103 and 104, and the well regions 101b and 102b.
Since the contact regions 107' and 108' are respectively substantially
formed in the same process as that for the p-type semiconductor regions
107a and 107b and the n-type semiconductor regions 108a and 108b and
formed integrally therewith, the illustration of these in FIG. 2 is
omitted for ease in understanding the drawing. Incidentally, chain lines
and two-dot chain lines in the objects, A, B, F and G shown in FIG. 3(A),
FIG. 3(B), FIG. 3(H) and FIG. 3(I), respectively, indicate border lines
indicative of the outside shapes of cells and do not indicate the
components that constitute the respective objects.
The design data for the objects A through H are developed as hierarchical
data called "plural layers" corresponding to a mask used in a production
process. For example, the removal of the object A means that information
about the layer constituting the object A is removed. A mask used in the
production process is created by synthesizing or combining together the
same data (hierarchical data) divided into or distributed to the objects A
through H. For example, the gate electrode 109p of the object CP and the
gate electrode 109n of the object CN are placed under the same layer
(hierarchical data). A mask pattern for forming the polysilicon gate
electrode 109 is formed by combining these hierarchical data together.
Further, the wiring 110 of the object DWL, the Vcc line 103 and Vss line
104 of the object G, and the VBP line 105 and VBN line 106 of the object A
are the same hierarchical data. A mask pattern for forming the metal layer
corresponding to the first layer is created by combining these
hierarchical data together. Thus, the design data for forming the same
mask pattern constitutes the same hierarchical data. In regard to the
inverter cell illustrated in the present embodiment, the same layer may be
associated with components or elements of different objects other than the
objects A and B.
When data obtained by eliminating the design data for the object A from the
cell design data for forming the CMOS inverter cell shown in FIG. 1 are
used (i.e., when the design data for the objects B through H are used), a
substrate potential fixed CMOS inverter INV having a circuit configuration
shown in FIG. 20(A) is constructed as shown in FIG. 4(A) wherein a Vcc
line 103 and a Vss line 104 are electrically connected to the n well
region 101 and the p well region 102 respectively. On the other hand, when
data obtained by removing the design data for the object B from the design
data for forming the CMOS inverter shown in FIG. 1 are used (i.e., when
the design data for the objects A, CN and CP through H are used), a
substrate potential variable CMOS inverter INV having a circuit
configuration shown in FIG. 21 (A) is constructed as shown FIG. 4(B)
wherein a VBP line 105 and a VBN line 106 are electrically connected to
the n well region 101 and the p well region 102 respectively.
That is, a library for a substrate potential fixed cell or a library for a
substrate potential variable cell can be formed by preparing the design
data having the objects A through H as a common cell layout and
eliminating the object A or B from the common cell layout. Thus, the term
common cell topology refers ti a method for forming two cell libraries
using one common cell pattern and an approach therefor or the like.
That is, one common cell pattern is considered as an aggregate of objects.
The two cell libraries can be formed from the common cell pattern by
adding predetermined objects thereto.
Even in the case of NOR gate circuits, NAND gate circuits, switch circuits
SW1 abd SW2, RAM, etc. similar to the inverter cell, a common layout for
logic circuit cells respectively comprising the NOR gate circuits, NAND
gate circuits, switch circuits SW1 and SW2, RAM, etc. can be configured by
suitably forming the objects CP, CN, DW, DTW, E, F and H.
Each cell library can be formed from the common cell pattern as a substrate
potential common cell library in a manner similar to the CMOS inverter
cell INV.
Further, the common layout pattern for each logic circuit cell includes
objects A and G each having cell heights Ha and Hb similar to those
employed in the common layout pattern for the aforementioned CMOS inverter
cell INV. Thus, when the logic circuit cells CELL using the substrate
potential variable cell library are arranged in a cell row direction as
shown in FIGS. 5(A), 5(B) and 5(C), their corresponding power supply lines
(103 through 106) are respectively integrally formed and configured so as
to extend in a cell direction.
That is, the substrate potential common library and the substrate potential
variable cell library are created from the common layout pattern for the
logic circuit cells. A desired logic circuit can be configured by opening
one library thereof and placing and connecting the logic circuit cells
CELL. In this case, the logic circuit cells CELL are arranged so as to
adjoin each other in the cell row direction. The power supply lines (103
through 106) are integrally formed in the cell direction as shown in FIGS.
5(A), 5(B) and 5(C). Similarly, when the logic circuit cells CELL are
disposed using the substrate potential fixed cell library in a cell row
direction, they are placed adjacent to each other in the cell row
direction and the power supply lines (103 and 104) are integrally formed
in the cell direction as illustrated in FIGS. 5(C) and 5(B).
When the substrate potential variable CMIS inverter cells CELL or the like
are selected, a substrate bias control circuit BVC for supplying bias
voltages Vbp and Vbn generated from a bias voltage generator BVC shown in
FIG. 5(A) or power sources Vcc and Vss to each inverter cell INV are
provided at a given position of a semiconductor chip and are controlled
according to control signals stb1 and stb2 so as to apply bias voltages
Vbp (=1.8V) and Vbn (=0V) so as to set a reverse bias voltage developed
between the source of MISFET and the substrate smaller than base
potentials Vbp (=3.3V) and Vbn (=-1.5V) at standby to each of the
individual well regions through a VBP line 105 and a VBN line 106 upon an
active state in place of the base potentials Vbp and Vbn as shown in Table
1, for example. As shown in FIG. 6(A), basic circuit cells CELL are
connected to one another in their cell directions by using wires or
interconnections of a metal layer defined as a first layer and a metal
layer defined as a second layer so as to constitute a desired logic
circuit.
In the aforementioned embodiment, the objects A and B may be prepared as an
aggregate of much smaller objects. Similar to the inverter cells referred
to above, cells comprised of basic logic circuits such as NAND gate
circuits, NOR gate circuits, etc. are designed so as to be capable of
constituting either a substrate potential fixed circuit or a substrate
potential variable circuit and may be registered in a library.
Alternatively, cells capable of constituting both the substrate potential
fixed circuit and the substrate potential variable circuit may be designed
in a memory such as a RAM or the like so as to be registered in a library.
Further, design information about the bias voltage generator BVG and
substrate bias control circuit BVC may be registered in cell libraries as
single circuit cells, respectively. In place of the mounting of the bias
voltage generator BVG on the semiconductor chip, the bias voltages Vbp and
Vbn may be supplied from the outside.
As is apparent from a comparison between FIG. 4(A) and FIG. 4(B) or a
comparison between FIG. 5(B) and FIG. 5(C), the substrate potential fixed
CMOS inverter cell shown in 4(A) is reduced in cell area by the VBP line
105 and the VBN line 106 as compared with the substrate potential variable
CMOS inverter cell shown in FIG. 4(B). Thus, when it is desired to form a
circuit that needs a high-speed operation, the substrate potential fixed
CMOS inverter cell is selected, whereby a reduction in chip size
preferentially can be achieved.
That is, when the substrate potential fixed cells CELL each shown in FIG.
4(A) are utilized in combination to form logic as shown in FIG. 5(C),
regions for the VBP line 105 and the VBN line 106 can be used as wiring
regions because the cell height Ha shown in FIG. 4 (A) is smaller than
that shown in FIG. 4(B). It is therefore possible to reduce the chip size
and provide high integration and high functioning. That is, since
intervals defined between cell rows, which extend in the direction normal
to a cell row direction, can be reduced in FIGS. 5(C) and 6(B), a
reduction in chip size and high integration can be achieved. The interval
between the adjacent power supply lines (103 and 104) employed in the
cells CELL is the same as that for the substrate potential fixed cell and
the substrate potential variable cell.
The configuration and operation of the substrate bias control circuit BVC
will next be described using FIG. 5(A) and Table 1.
The substrate bias control circuit BVC employed in the present embodiment
comprises a first switch circuit SW1 comprised of a p channel MISFET Qp1
which is provided between the VBP line 105 employed in the embodiment
shown in FIG. 1 as a substrate potential supply line and the bias voltage
generator BVC and which is controlled by a control signal/stb1, and an n
channel MISFET Qn1 provided between the VBN line 106 used as a substrate
potential supply line and the bias voltage generator BVG and controlled by
a control signal stb2, and a second switch circuit SW2 comprised of a p
channel MISFET Qp2 provided between the Vcc line 103 and the VBP line 105
and controlled by a control signal stb1, and an n channel MISFET Qn2
provided between the Vss line 104 and the VBN line 106 and controlled by a
control signal/stb2.
The second switch circuit SW2 is provided one by one per a predetermined
number of basic circuit cells (inverter cells or NOR or NAND logic
circuits (gates)), that is, a plurality of the second switch circuits SW2
are provided for each cell row CR. The first switch circuit SW1 is
provided as a circuit common to the plurality of second switch circuits
SW2. Thus, the MISFETs Qp1 and Qn1 constituting the first switch circuit
SW1 are designed so as to be greater than the MISFETs Qp2 and Qn2
constituting the second switch circuit SW2 in device size. It is desirable
for the pitch of placement of each second switch circuit SW2 to be reduced
according to the operating frequency of an LSI and wiring resistances of
the power supply Vcc and Vss lines 103 and 104 as the operating frequency
increases and a voltage drop becomes great, thereby increasing the number
of the second switch circuits SW2 provided within one cell row CR. It is
thus possible to reduce a variation in substrate potential incident to a
circuit operation and prevent the circuit from operating due to noise.
Thus, a desired logic circuit is configured by placing the basic circuit
cells CELL and providing a connection between the basic circuit cells CELL
using the wires or interconnections of the metal layers 110' and 110"
corresponding to the first and second layers. Incidentally, the logic
circuit may be configured by placing a plurality of cell rows CR as shown
in FIG. 6(A). In this case, the first switch circuit SW1 may be provided
every cell rows CR. Alternatively, one cell row CR may be provided for the
logic circuit as shown in FIG. 6(A). As shown in FIGS. 6(A) and 6(B), the
intervals defined between the adjacent cell rows CR are used as wiring
regions and connections between the cell rows or within each cell are made
by using the interconnections of the metal layers 110' and 110"
corresponding to the first and second layers.
Further, the substrate bias control circuit BVC sets the control signals
stb1,/stb1, stb2 and/stb2 to Vss (=0V), Vbp (=3.3V), Vbn (=-1.5V) and Vcc
(=1.8V) respectively. Thus, the MISFETs Qp1 and Qn1 of the switch SW1 are
turned off and the MISFETs Qp2 and Qn2 of the switch circuit SW2 are
turned on so that the source voltages Vcc and Vss are respectively
supplied to the VBP and VBN lines 105 and 106 connected to their
corresponding inverter cells INV. Thus, each MISFET of the inverter cell
INV undergoes or receives a low reverse bias voltage between the source
thereof and the substrate to reduce its threshold, whereby it operates at
high speed.
TABLE 1
Active Standby
Power Vcc Voltage 1.8 V
Source Vss Voltage 0.0 V
Vbp Voltage -- 3.3 V
Vbn Voltage -- -1.5 V
Control stb1 L(0.0) H(3.3)
Signal stb1 H(3.3) L(0.0)
stb2 L(-1.5) H(1.8)
stb2 H(1.8) L(-1.5)
Controlled VBP line Vcc(1.8) Vbp(3.3)
Power VBN line Vss(0.0) Vbn(-1.5)
On the other hand, the control signal stb1 is set to Vbp (=3.3V), the
control signal/stb1 is set to Vss (=0V), the control signal stb2 is set to
Vcc (=1.8V) and the control signal/stb2 is set to Vbn (=-1.5V),
respectively upon non-operation of the circu | | |
