A semiconductor chip package having an internal laterally curved lead in order to compensate for the CTE mismatch between a semiconductor chip and a supporting substrate, such as a PWB.
This application is a divisional application of application Ser. No. 09/120,006 filed on Jul. 21, 1998 now U.S. Pat. No. 6,265,759 which is a divisional application of application Ser. No. 08/709,127, filed on Sep. 6, 1996, now U.S. Pat. No. 5,821,608, which claims Provisional Patent Application No. 60/003,424 filed on Sep. 8, 1995.
A method of making a semiconductor package device includes attaching a semiconductor chip to a metallic structure using an insulative adhesive, wherein the chip includes a conductive pad, the metallic structure includes first and second opposing surfaces and a lead, the adhesive is disposed between the first surface and the chip, the lead includes a recessed portion, a non-recessed portion and opposing outer edges between the first and second surfaces that extend across the recessed and non-recessed portions, and the recessed portion is recessed relative to the non-recessed portion at the second surface, forming an encapsulant that contacts the chip, the first surface, the outer edges and the recessed portion, wherein the encapsulant completely covers the chip, the outer edges and the recessed portion without completely covering the non-recessed portion, and forming a connection joint that electrically connects the lead and the pad.
A semiconductor package device includes an insulative housing, a semiconductor chip, a terminal and a lead, wherein the insulative housing includes a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, the chip includes a conductive pad, the terminal protrudes downwardly from and extends through the bottom surface and is electrically connected to the pad, the lead protrudes laterally from and extends through the side surface and is electrically connected to the pad, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another inside the insulative housing and outside the chip.
A method of testing a semiconductor package device includes providing a device that includes an insulative housing, a semiconductor chip, a terminal and a lead, wherein the terminal protrudes downwardly from and extends through a bottom surface of the housing, the lead protrudes laterally from and extends through a side surface of the housing, and the terminal and the lead are electrically connected to one another and a chip pad inside the housing, attaching the device to a test socket that electrically contacts the lead without electrically contacting the terminal, testing the test socket, and removing the device from the test socket. The method may include trimming the lead after removing the device from the test socket and the attaching the device to a printed circuit board that electrically contacts the terminal without electrically contacting the lead.
An optoelectronic semiconductor package device includes a semiconductor chip, an insulative housing and a conductive trace, wherein the chip includes an upper surface and a lower surface, the upper surface includes a light sensitive cell and a conductive pad, the insulative housing includes a first single-piece non-transparent insulative housing portion that contacts the lower surface and is spaced from the light sensitive cell and a second transparent insulative housing portion that contacts the first housing portion and the light sensitive cell, and the conductive trace extends outside the insulative housing and is electrically connected to the pad inside the insulative housing.
A semiconductor package device includes an insulative housing, a semiconductor chip, and a lead, wherein the insulative housing includes a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, the bottom surface includes a peripheral portion and a central portion within the peripheral portion, the peripheral portion protrudes downwardly from the central portion, the chip includes a conductive pad, and the lead protrudes laterally from and extends through the peripheral side surface and is electrically connected to the pad.
