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Semiconductor device and method of manufacturing the same
   
Document Number
US Patent 6476496
Issued Date
November 5, 2002
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Abstract
An interconnection forming step provides an interconnection with an improved yield, a low cost and a high reliability. A semiconductor device includes an insulating layer formed on a silicon substrate and having a groove extending in a predetermined direction. A distance between side walls defining insulating layer increases as a position moves away from silicon substrate. The semiconductor device includes a conductive layer filling groove.
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Semiconductor device and method of manufacturing the same - US Patent 6476496 Drawing
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Number of Claims:
7
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Published
November 5, 2002
Application Number
09/461,377
Filed
December 15, 1999
US Classification
257/774   257/E21.578 257/E21.589
Int'l Classification
H01L   21/70   (20060101)   H01L   21/768   (20060101)  
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Priority Data
Jun 28, 1999 [JP] 11-181469
USPTO Field of Search
257/774  
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