System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpr

What is claimed is:

1. An input/output interface circuit for a semiconductor chip, the input/output interface circuit comprising:

an output buffer circuit operable to receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements; and

an input buffer circuit operable to receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

2. The input/output interface circuit of claim 1 wherein the output buffer circuit is operable to control the skew of the first data transmission signal.

3. The input/output interface circuit of claim 1 wherein the output buffer circuit is operable to drive the first data transmission signal.

4. The input/output interface circuit of claim 1 wherein the output buffer circuit comprises:

a data encoder circuit operable to encode the first stream of data elements;

a slew rate control circuit coupled to the data encoder circuit, the slew rate control circuit operable to control the slew rate of an output driver circuit when transmitting the first data transmission signal; and

an output driver circuit coupled to the slew rate control circuit, the output driver circuit operable to drive the first data transmission signal.

5. The input/output interface circuit of claim 1 wherein the input buffer circuit comprises a sample and hold circuit operable to sample voltages values for each data element of the second stream and the respective reference element, the sample and hold circuit operable to compare the sampled voltage for each data element of the second stream against the sampled voltage for the respective reference element.

6. The input/output interface circuit of claim 1 wherein the first and second data transmission signals are formatted according to a two-level scheme wherein two signal levels are available to represent each data element and each reference element.

7. The input/output interface circuit of claim 1 wherein the first and second data transmission signals are formatted according to a three-level scheme wherein a first and second signal levels are available to represent each data element and a third signal level is used to represent each reference element.

8. A method for interfacing between a first semiconductor chip and a second semiconductor chip, the method comprising:

receiving a stream of data elements for output from the first semiconductor chip;

adding a separate reference element for each data element in the stream;

generating a data transmission signal representing the data elements of the stream and the respective reference elements;

transmitting the data transmission signal out of the first semiconductor chip and to the second semiconductor chip.

9. The method of claim 8 further comprising:

receiving the data transmission signal at the second semiconductor chip;

sampling the data transmission signal to obtain voltage values for each data element of the data stream and the respective reference element; and

interpreting the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the data stream at the second semiconductor chip.

10. The method of claim 9 wherein sampling comprises:

latching a voltage value for each data element at a first node; and

latching a voltage value for each respective reference element at a second node.

11. The method of claim 9 wherein interpreting comprises comparing the voltage value for each data element against the voltage value for the respective reference element.

12. The method of claim 8 wherein the data transmission signal is formatted according to a two-level scheme wherein two signal levels are available to represent each data element and each reference element.

13. The method of claim 8 wherein the data transmission signal is formatted according to a three-level scheme wherein a first and second signal levels are available to represent each data element and a third signal level is used to represent each reference element.

14. A method for interfacing with a semiconductor chip comprises:

receiving a data transmission signal representing data elements of a data stream and respective reference elements for the data elements of the data stream;

sampling the data transmission signal to obtain voltage values for each data element of the data stream and the respective reference element; and

interpreting the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the data stream.

15. The method of claim 14 wherein sampling comprises:

latching a voltage value for each data element at a first node; and

latching a voltage value for each respective reference element at a second node.

16. The method of claim 14 wherein interpreting comprises comparing the voltage value for each data element against the voltage value for the respective reference element.

17. The method of claim 14 wherein the data transmission signal is formatted according to a two-level scheme wherein two signal levels are available to represent each data element and each reference element.

18. The method of claim 14 wherein the data transmission signal is formatted according to a three-level scheme wherein a first and second signal levels are available to represent each data element and a third signal level is used to represent each reference element.

19. A semiconductor chip comprising:

a timing circuit operable to generate a plurality of timing signals; and

an input/output interface circuit coupled to the timing circuit and receiving at least one timing signal from the timing circuit, the input/output interface circuit operable to receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements.

20. The semiconductor chip of claim 19 wherein the input/output interface circuit is operable to receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

21. The semiconductor chip of claim 19 comprises a separate synchronous clock generator circuit, the synchronous clock generator circuit operable to cooperate to provide a synchronous clock signal.

22. An integrated circuit device comprising:

a plurality of semiconductor chips; and

a central access hub coupled to each of the semiconductor chips, the central access hub operable to receive a first stream of data elements for output from the integrated circuit device, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements.

23. The integrated circuit device of claim 22 wherein the central access hub is operable to receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

24. The integrated circuit device of claim 22 wherein each semiconductor chip comprises a memory chip.

25. The integrated circuit device of claim 22 wherein the central access hub comprises at least one input/output interface circuit implementing a correlated double-sampling technique for transmitting and receiving data transmission signals.

26. The integrated circuit device of claim 22 wherein each of the semiconductor chips and the central access hub comprises a separate synchronous clock generator circuit, the synchronous clock generator circuits operable to cooperate to provide a synchronous clock signal throughout the integrated circuit device.

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TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to the field of semiconductor integrated circuits, and more particularly, to input/output interfacing for a semiconductor chip.

BACKGROUND OF THE INVENTION

Data input into or output from an integrated circuit (IC) device is represented by a sequence of varying voltage values appearing in an appropriate signal. For data that is output from an IC device, the voltage level for a logical "0" (logic-0) is generally referred to as "voltage output low" or "V.sub.OL," while the voltage level for a logical "1" (logic-1) is generally referred to as "voltage output high" or "V.sub.OH." For data that is input into an IC device, the voltage level for a logic-0 is generally referred to as "voltage input low" or "V.sub.IL," while the voltage level for a logic-1 is generally referred to as "voltage input high" or "V.sub.IH."

For the signals which communicate data to and from an IC device, a reference voltage (V.sub.REF) may define how the sequence of voltage values in each signal should be interpreted or construed in order to derive the represented data. Furthermore, suitable margins above and below the reference voltage are provided for interpretation of the signals.

Various industry-standard, interface signaling technologies have been developed for transmitting data to and from an IC device. These signaling technologies include transistor-to-transistor logic (TTL), low-voltage TTL (LVTTL), stub-series terminated logic (SSTL_3 or SSTL_2), and RAMBUS signaling level (RSL).

The logic-0 (V.sub.IL and V.sub.OL) and logic-1 (V.sub.IH and V.sub.OH) voltage levels are different for each interface signaling technology. TTL and LVTTL have relatively large signal swings and do not require a reference voltage to determine whether the data under transfer is either a logic-0 or a logic-1. SSTL_2, SSTL_3 and RSL have smaller signal swings (0.8-1.2 volts) for high speed data transfer, and require a reference voltage for interpreting data. RSL utilizes an open-drain output driver with external pull-up termination resistor connected to a termination voltage V.sub.TT. The following chart provides values for the voltage levels of the various interface signaling technologies. VIH VIL VOH VOL VREF VTT VDDQ TTL 2.4 V 0.8 V 2.4 V 0.8 V N/A N/A 5 V LVTTL 2.0 V 0.8 V 2.0 V 0.8 V N/A N/A 3.3 V SSTL-3 VREF + VREF - VTT + VTT - 1.5 .+-. 1.5 .+-. 3.3 V 0.4 V 0.4 V 0.6/0.8 V 0.6/0.8 V 0.2 V 0.05 V SSTL-2 VREF + VREF - VTT + VTT - 1.25 .+-. VREF .+-. 2.5 V 0.35 V 0.35 V 0.57/ 0.57/0.76 V 0.1 V 0.04 V 0.76 V RSL 1.8 V 1.0 V 1.8 V 1.0 V 1.4 V 1.8 V 2.5 V Note: (1) All numbers listed in the chart above are typical values. (2) VDDQ is the power supply for data output driver.

The use of a reference voltage (V.sub.REF) to determine the logic level of data with some interface signaling technologies (i.e., those having a small signal swing) presents many disadvantages. For example, a number of different factors--such as varying internal supply voltage or reference voltage, or noise created at one or more voltage drivers--can cause the value of the signal levels (e.g., V.sub.OH, V.sub.OL, V.sub.IH, V.sub.IL) to drift or change. This results in a loss of signal margin during operation, which ultimately can lead to problems with data integrity. Furthermore, with previously developed interface technologies, the signal levels of logic-1 and logic-0 are not scaleable. This sets constraints on the bandwidth of data transfer. Also, because signal levels are not scalable, the interface technologies are plagued with high power consumption and significant switching noise. This in turn causes problems in designing systems in which semiconductor integrated circuits with different electrical I/O interface specifications are used, due to the scaling down of design rules and lithography of the integrated circuits. In addition, previously developed interface technologies utilize a high data slew rate that causes electromagnetic interference (EMI) problem, especially when a wider data bus is desirable to meet the bandwidth requirements of a high performance system. Accordingly, it is difficult to achieve appropriate data setup and hold times for high data rate operation.

SUMMARY OF THE INVENTION

The disadvantages and problems associated with previously developed interfaces for an integrated circuit device have been substantially reduced or eliminated using the present invention.

According to the present invention, a correlated double-sampling (CDS) technique is provided for the input and output of data in a semiconductor chip. For each element (e.g., bit) of data in an outgoing data stream, the technique adds a separate reference element. The data elements and respective reference elements are represented by corresponding voltage values in a transmission signal output by the semiconductor chip. When the transmission signal is received by another semiconductor chip, it is sampled for both the data elements and the respective reference elements--hence, the term "double-sampling". Each reference element is used to interpret the corresponding data element so that the data element can be recovered. For example, in one embodiment, the data element may be compared against the respective reference element.

An input/output (I/O) interface circuit, according to one embodiment of the present invention, implements the CDS technique. For output from a semiconductor chip, the CDS I/O interface circuit adds a reference element for each data element in an outgoing data stream. The CDS I/O interface circuit generates a transmission signal in which the data elements and respective reference elements are represented by corresponding voltage values. The transmission signal is sent out from the semiconductor chip. For input into the semiconductor chip, the CDS I/O interface circuit receives a transmission signal wherein various voltage values represent a number of data elements and respective reference elements. The CDS I/O interface circuit samples the received signal for the data elements and reference elements. The CDS I/O interface circuit interprets each data element using the respective reference element.

In accordance with one embodiment of the present invention, an I/O interface circuit for a semiconductor chip is provided. The I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

In accordance with another embodiment of the present invention, a method for interfacing between a first semiconductor chip and a second semiconductor chip includes the following steps: receiving a stream of data elements for output from the first semiconductor chip; adding a separate reference element for each data element in the stream; generating a data transmission signal representing the data elements of the stream and the respective reference elements; transmitting the data transmission signal out of the first semiconductor chip; receiving the data transmission signal at the second semiconductor chip; sampling the data transmission signal to obtain voltage values for each data element of the data stream and the respective reference element; and interpreting the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the data stream at the second semiconductor chip.

In accordance with yet another embodiment of the present invention, an integrated circuit device includes a number of semiconductor chips. A central access hub, coupled to each of the semiconductor chips, receives a stream of data elements for output from the integrated circuit device. The central access hub adds a separate reference element for each data element in the stream and generates a data transmission signal representing the data elements and the respective reference elements.

An important technical advantage of the present invention includes providing a separate reference element for each data element in an outgoing data stream. The data and reference elements are represented by corresponding voltage values in a transmission signal output from a semiconductor chip. At another semiconductor chip which receives such signal, the signal is sampled for the data elements and reference elements. Each reference element can be used to interpret the respective data element. Because the data elements are interpreted against respective refe