A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.
A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.
A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.
A cache memory with improved cache-miss performance is implemented by providing cache-miss data from system memory directly to its requester. One embodiment of the invention operates as a texture cache in a graphics system. The graphics system comprises a system memory that stores texture data, coupled to a texture cache memory, which is coupled to at least one requester. The texture cache memory is divided into a cache tags unit and a data cache unit. The data cache unit is configured to receive at least two cache address inputs, and has at least two data output ports each coupled to a respective first input of a respective multiplexer. A respective second input of each multiplexer is configured to receive cache-miss data from the system memory. The select input of each multiplexer is configured to receive a respective hit/miss indicator signal associated with the respective cache address input. In case of a cache-miss, cache-miss data from system memory bypasses the data cache unit and is output directly. The cache-miss data is then written into the data cache unit during a subsequent clock cycle.
The decision to prefetch inodes is based upon the detecting of access patterns that would benefit from such a prefetch. Once the decision to prefetch is made, a plurality of inodes are prefetched in parallel. Further, the prefetching of inodes is paced, such that the prefetching substantially matches the speed at which an application requests inodes.
A computer system and a method used to test and repair defective memory portions of memory devices located on a memory module. The computer system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub comprises a self-test module that determines the locations of defective memory locations of the memory devices. A repair module also included in the memory hub uses the locations of defective memory portions to create a remapping table. The remapping table redirects accesses to the defective locations of the memory devices to non-defective memory locations. Each time the memory hub receives a memory request from a memory access device, the memory hub checks the memory location to which the access is directed, and, if necessary, redirects the memory access to a non-defective location.
