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Method of controlling cache memory in multiprocessor system and the multiprocessor system based on detection of predetermined software module
   
Document Number
US Patent 6480940
Issued Date
November 12, 2002
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Abstract
Cache control protocols can be switched during running without changing an architecture for a segment descriptor or page descriptor for indicating an attribute of an area to be accessed. A plurality of processors each including a cache memory constitute a multiprocessor system which shares a main memory via a system bus. Each processor has module detecting means for detecting execution of a module which accesses a shared memory area on the main memory, by comparing the virtual space number and the instruction segment number concerning the accessing module with those numbers concerning the software modules preset which may access the shared memory area. Memory access executed in a module detected by the module detecting means is controlled in a cache control protocol of a store-through scheme which updates a main memory simultaneously with update of a cache memory. Memory access executed in other modules is controlled in a cache control protocol of a store-in scheme which does not update a main memory at update of a cache memory.
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Number of Claims:
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Owner
NEC Corporation (Tokyo,JP)
Published
November 12, 2002
Application Number
09/429,329
Filed
October 28, 1999
US Classification
711/141   711/147 711/3
Int'l Classification
G06F   12/08   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Oct 30, 1998 [JP] 10-326050
USPTO Field of Search
711/141   711/142   711/143   711/144   711/145   711/146   711/128   711/119   711/120   711/121   711/125   711/3   711/208   711/147  
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Description
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