An electronic device under test (DUT) may be incorporated into a circuit having a voltage limiter connected in parallel with the DUT. The circuit includes a controlled current source having an output current connected in series with the DUT. The voltage limiter is characterized in that, when the output current is such that the voltage across the DUT (Vdut) would exceed a particular maximum voltage Vmax, without the voltage limiter in place, at least a portion of the output current flows through the voltage limiter, so as to limit Vdut to be less than or equal to Vmax. When the output current is such that Vdut would be less than or equal to Vmax, current does not flow through the voltage limiter. The circuit may include a plurality of DUTs, each DUT connected in series with the output current of a controlled current source, with a voltage limiter connected in parallel with each DUT.

The invention provides a test device for testing circuit units (101a 101n) to be tested, having connecting units (106a 106n) for connecting the circuit units (101a 101n) to be tested to the test device, a test system (100) and an output unit (108) for outputting test result data, the test device having a determining unit (103) for determining those of the measurement data (110a 101n) which correspond for a predeterminable number of circuit units (101a 101n) to be tested, and for defining the corresponding measurement data (110a 110n) as the expected data (111); and comparison units (104a 104n) for comparing the measurement data (110a 110n) generated by the circuit units (101a 101n) to be tested in a manner dependent on the test data (112) written in with the expected data (111) in order to obtain comparison data (115a 115n).

A semiconductor chip test system and test method thereof are provided. The system having a plurality of data input/output pins, a tester for inputting/outputting data through the plurality of data input/output pins; a plurality of semiconductor chips to be tested by the tester; a control circuit for sequentially outputting the output data from each of the plurality of semiconductor chips to the tester during a read operation and simultaneously supplying the input data from the tester to the semiconductor chips during a write operation.

Each of a system for qualifying a multiple die under test head and a system for qualifying the multiple die under test head employ selection of a sub-set of die arrays within a calibration standard substrate. The sub-set of die arrays is selected such as to: (1) not overlap in position within the calibration standard substrate; and (2) have in an aggregate no greater than one defective die within each of a series of die locations. The system and the method provide for accurate and efficient qualification of the multiple die under test head and thus accurate and efficient electrical test measurement of a microelectronic product.

An apparatus and method for debugging a bus including interposing a device that monitors the data transferred between two devices on the bus such that the bus is split into two busses, with data being copied for transmission to a diagnostics device as the data is transferred between the two busses.