A semiconductor integrated-circuit device includes both conventional internal circuitry, and a selection circuit that provides external output of signals from the internal circuitry under control of a selection signal. In a parallel test system, the output terminals of a plurality of devices under test are connected to a single set of tester input terminals, at which response signals are received from each device in turn. Alternatively, each device has an internal test circuit that carries out tests in response to test control codes received from a tester, evaluates the response signals from the internal circuitry, makes a pass/fail decision, and provides the tester with the pass/fail result.
Method and system for shortening the time needed to test a semiconductor device having a plurality of memory circuits. The semiconductor device includes an address decoder for selecting a plurality of memory circuits and causing the memory circuits to perform a read/write operation. A comparator receives plural pieces of read data read from the plurality of memory circuits and compares the plural pieces of read data with one another. A processing unit compares one of the plural pieces of read data with write data. Using the comparison results of the comparator and the processing unit shorten the time needed to test the plurality of memory circuits.
A method for managing testing of test material is disclosed. An electronic traveler associated with the test material is identified. The test materials are tested as specified by the electronic traveler. Test results from the tests are recorded onto the electronic traveler.
An integrated circuit (IC) chip contains a small non-volatile "ID" memory such as an FeRAM array that stores information associated with manufacturing, testing, and performance of the IC chip. The stored information can include but is not limited to a serial number, a wafer ID, a batch ID, a date code, chip history, test data, and performance information. The storing information on the chip eliminates any difficulty in matching the information with the IC chip and provides a flexible permanent record of any information the manufacturer may find useful. The ID memory thus permits tracking and identification of ICs to a degree that was not previously practical. Additionally, a self-test can compare prior test results stored in the ID memory to current self-test results to detect defects or to select operating parameters of the integrated circuit.
A system for testing a synchronous link utilizing a single test pattern sequence. Components coupled via a link are each configured to generate and check test patterns according to a single repeated test pattern sequence. Test patterns which are generated are based upon two simple patterns. Each test cycle, a bit is chosen from one of the two patterns for use in generating the test pattern. A sixteen cycle test pattern sequence is utilized in which values are chosen from one or the other of the two patterns in a predetermined manner. In a bi-directional test, two components which are coupled via a link alternate driving selected values based upon the predetermined sequence. Each component may alternate driving sequences of one or more cycles. An ordering of cycles may be chosen to test various permutations of driver interaction between the respective components.
