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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of integrated circuit testing.
2. Description of the Related Art
An integrated circuit (IC) is a miniature electric circuit containing large numbers of discrete electronic circuit elements, such as transistors, resistors, capacitors, and diodes, which are packaged as a single unit with leads extending from it
for input, output, and power-supply connections. The electronic circuit elements are formed by selective manipulation of a single chip of semiconductor material, often in combination with various other semi-conducting and/or conducting materials.
It is common in the art to roughly classify integrated circuits dependent upon their transistor density. Presently, there are effectively four common integrated circuit classifications: small-scale integrated circuits (SSIs); medium-scale
integrated circuits (MSIs); large-scale integrated circuits (LSIs); and very-large-scale integrated circuit (VLSIs). Exactly what transistor densities constitute the various "classes" varies, but at present SSIs typically include up to several tens of
transistors, MSIs include from many tens to several hundred transistors; LSIs include from several hundred to a few thousand transistors; and VLSIs several hundred thousand or more. Most ICs in use today would constitute VLSIs.
One powerful feature of integrated circuits is the ability to use such integrated circuits to produce several levels of abstraction, which is useful for complete design. For example, integrated circuit design can be viewed at one level of
abstraction in terms of discrete electronic circuit components (e.g., resistors, capacitors, inductors, transistors, diodes, etc.). Integrated circuit design can also be viewed at a next-higher layer of abstraction in terms of logic diagrams consisting
of well-defined digital Boolean logic circuits such as AND, NAND, OR, and NOR gates, where each such gate consists of well-defined congeries of the discrete electronic circuit elements. Integrated circuit design can also be viewed at yet a next-higher
layer of abstraction known as Register Transfer Level (RTL), which consists of program-like statements describing the movement or processing of data between storage elements. Integrated circuits can also be viewed at a yet again higher layer of
abstraction known as a functional block diagram layer, which shows the major subcomponents of a design. This is the level at which the highest conceptual design work is done.
Typically, IC design is done at the functional block diagram, RTL, and logic diagram levels. It is common for whole teams of people (and sometimes whole companies) to focus on various aspects of the design at various abstraction levels.
However, as noted, the design process rarely proceeds at a lower level than that of logic diagrams. Below this level, it is common to program the desired logic diagram layouts into artificially intelligent software, which automatically produces discrete
circuit component level diagrams to be enacted within the integrated circuit.
As noted above, the discrete circuit level components are produced via the selective manipulation of a single piece of semiconductor material, where such selective manipulation usually includes the use of other semi-conducting and/or conducting
materials. The discrete circuit level components are created via this selective manipulation.
The regions affected by the selective manipulation of the single piece of semiconductor material are almost unimaginably small. For example, current VLSI production procedures produce the discrete circuit components by manipulating material by
use of sub-micron width (i.e., widths of less that (1/1,000,000) of a meter) lines drawn, or "etched," in the semiconductor material. Furthermore, the sizes of the regions manipulated decrease virtually every week.
Due to the very small regions manipulated during VLSI production, errors invariably occur. This can be the result of contamination of the material, or minor variations in the length, width, or height of lines etched. These errors in production
often result in errors in the behavior of the discrete electronic circuit level components.
As noted, the higher abstraction logic diagram level is designed using logic diagram level component circuits consisting of congeries of discrete circuit level components. Consequently, errors in production sufficient to produce errors in the
behavior of the discrete circuit level components can "propagate" upwards to the logic diagram level since the logic diagram circuits are built from congeries of these malfunctioning circuit components. If the errors are severe, then such malfunctioning
will be very apparent in that the affected logic diagram level circuits will not function. However, if the malfunction is not severe, it is possible that the affected logic diagram level components will perform, but will perform in such a way that is
out of design tolerances, which can cause a general system malfunction or failure as these logic diagram level errors "propagate" up the abstraction-layer hierarchy to affect the RTL and functional block diagram level designs.
A principal way in which such a malfunction will manifest at the logic diagram level is that one or more of the logic diagram level circuits will perform their functions appropriately, but so slowly that they affect the design. Accordingly,
testing has been devised in the art to ensure that the logic diagram level circuits are performing their functions within design tolerances. This testing basically amounts to the following: (1) defining at least one combinational logic path through a
combinational logic circuit; (2) initializing the combinational logic circuit with a given set of inputs; (3) waiting until the combinational logic circuit becomes stable; (4) changing the logic levels of one or more of the set of inputs; and (5) and
measuring the time it takes for output of the combinational logic circuit at the end of the defined path to change subsequent to the change in the set of inputs.
With reference now to FIGS. 1A, 1B, and 1C, shown is combinational logic circuit 100 composed of logic diagram level circuits 108, 110 which will be utilized to illustrate how delay testing of combinational logic diagram circuits is achieved in
the related art. The diagrams in FIGS. 1A, 1B, and 1C show a combinational logic path that implements the equation output signal Z=(input signal a*input signal b)+input signal c, with the path from input signal a to output signal Z, whose delay is to be
measured, illustrated by the heavier dark line segments of path 102, 104, 106. As described above, two input signal test patterns are needed to measure the delay path: a first input signal test pattern to initialize output signal Z, and a second input
signal test pattern to cause a change in output signal Z from that to which it was previously initialized.
Depicted is that feeding combinational logic circuit 100 is scan chain register bank 101 composed of Registers a, b, and c. As has been discussed, scan chain test patterns need to be utilized to test the delay associated with path 102, 104, 106.
Such scan chain test patterns are typically generated by recognizing that the various logic circuits providing inputs to the path whose delay is to be tested generate certain requirements relevant to such scan chain patterns. For example, regarding AND
gate 108, in the context of controlling the value of output Z, those skilled in the art will recognize that a non-controlling logic value is logic 1. Furthermore, those skilled in the art will also recognize that, in the context of controlling of output
Z, a non-controlling value is logic 0 for OR gate 110. Consequently, to test the delay of path 102, 104, 106 both input signals from Register b and input signal from Register c should stay at non-controlling values, while input signal from Register a
should change from logic value 0 to logic value 1, or change from logic value 1 to logic value 0, in order to force a change in output signal Z. Two examples of test pattern sequences that satisfy the above conditions are as follows: a first test pattern
set of ABC=<initialization test pattern of "010", change input test pattern of "110">, or a second test pattern set which is the partial complement of the first test pattern set, ABC=<initialization test pattern of "110", change input test
pattern of "010">. The first test pattern set is illustrated in FIG. 1A.
Referring now to FIG. 1B, those skilled in the art will recognize that during the shifting of data through scan chain register bank 101, Register b(t+1)=Register a(t) and Register c(t+1)=Register b(t), where the value t is defined as clock cycle
count, which is illustrated as clock cycle waveform 112 in FIG. 1C. For sake of illustration, it will be assumed herein that values are clocked into registers at the leading edge of clock cycles in clock cycle waveform 112. However, those skilled in
the art will recognize that multitudinous variants on this scheme are possible.
Illustrated in FIG. 1B is that initialization test pattern "010" has been previously loaded into Registers a, b, and c. This input initializes combination logic path 100 and forces output Z=0. As shown, it is desired to use change input test
pattern "110" to test the delay of path 102, 104, 106.
As shown in FIG. 1C, it takes three leading-edge clock cycles before change input test pattern "110" can be fully clocked into Registers a, b, and c. Notice that since during the shifting of data through scan chain register bank 101, Register
b(t+1) =Register a(t) and Register c(t+1)=Register b(t), where the value t is defined as clock cycle count, there is no practicable way in which change input test pattern "110" can be clocked into scan chain register 101 in one clock cycle. Rather, on
the first leading edge Register a, b, and c contain "001", and on the second leading edge Register a, b, and c contain "101". Thereafter, on the third leading edge change input test pattern "110" is clocked into Registers a, b, and c. Thus, as
demonstrated, under the scheme shown, there is no practicable way to apply change input test pattern "110" immediately subsequent to initialization test pattern "010" in that intermediate patterns "001" and "101" must be clocked through Registers a, b,
and c in order to get change input test pattern "110" loaded into Registers a, b, and c subsequent to initialization test pattern "010" being loaded.
As the foregoing has shown, under the related art somewhat more than 3 clock cycles must elapse subsequent to initialization test pattern "010" being loaded into scan chain register bank 101 before change input test pattern "110" is loaded.
Those skilled in the art will recognize that, due to the foregoing noted difficulties, it is the practice within the related art to design scan chain test pattern sets dependent upon the inputs of any particular circuit under test, which thus severely
limits the number of test pattern sets which can be utilized. To use scan chain register bank 101 to illustrate this practice, notice that an initialization test pattern of "111" followed by a "0" could be utilized to apply the change input test pattern
"011"; notice also that the complement of the foregoing ("000" followed by a "1") could also be so applied with adequate results.
Notice that the test patterns which may be applied under the related art are wholly constrained by the arrangement of inputs of the combinational logic circuit under test and the fact that the test patterns are sequentially scanned into any scan
chain register. Those skilled in the art will recognize that it is quite possible, under the foregoing noted related art constraints, that there will be no scan chain test pattern sets that can be applied to test certain circuits. Those skilled in the
art will also recognize that even in those instances under the related art where a circuit under test does allow the construction of test pattern sets which can be practicably applied to the circuit, that the number and type of those test patterns will
be a severely constrained subset of all the test patterns that can be envisioned (a fact illustrated in relation to scan chain register bank 101, above).
Those skilled in the art will recognize that it is desirable to have the ability to practicably apply the full range of test pattern sets which may be appropriate to any particular combinational logic circuit under test, such as combinational
logic circuit 100. However, it has been demonstrated that under the related art it is not possible to practicably apply the full range of test pattern sets appropriate to a particular combinational logic circuit under test. It is therefore apparent
that a need exists in the art for a method and apparatus which will provide the ability to practicably apply the full range of test pattern sets appropriate to any particular combinational logic circuit under test.
SUMMARY OF THE INVENTION
A method and apparatus have been devised which provide the ability to practicably apply the full range of test pattern sets appropriate to any particular combinational logic circuit under test. The method and apparatus couple a change input scan
chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is
achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test pattern set from the change input and the initialization
scan chain test pattern.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any
way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
FIGS. 1A, 1B, and 1C illustrate how delay testing of combinational logic diagram level circuits is achieved in the related art.
FIGS. 2A, 2B, and 2C illustrate the functioning of embodiments of the present invention wherein shadow registers are utilized.
FIGS. 3A, 3B, and 3C, 3D and 3E illustrate embodiments of the present invention which will provide the advantage of the embodiments of FIGS. 2A, 2B, and 2C, but which utilize preexisting IC registers to provide the functions of shadow registers.
FIGS. 4, 5, 6A, 6B, 7A and 7B illustrate embodiments of the present invention which require near minimal numbers of shadow registers to achieve the ability to clock in a change input scan chain test pattern utilizing only one clock cycle.
The use of the same reference symbols in different drawings indicates similar or identical items.
DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
The following sets forth a detailed description of the best contemplated mode for carrying out the invention as described in the claims. The detailed description is intended to be illustrative and should not be taken as limiting.
Referring now to FIGS. 2A, 2B, and 2C shown is a combinational logic circuit 200 composed of logic diagram level circuits which will be utilized to illustrate the functioning of embodiments of the present invention. Depicted in FIG. 2A is that
shadowed scan chain register bank 201 is feeding combinational logic circuit 200. As shown, shadowed scan chain register bank 201 has Registers a, b, and c of scan chain register bank 101; however, also shown is that shadowed scan chain register bank
201 has "shadow" Register b' inserted between Registers a and b, shadow Register c' inserted between Registers b and c, and shadow Register a' inserted to be the input register, and thus is shown inserted to the left of Register a.
As will be shown in the discussions of FIGS. 2B and 2C, shadow Registers a', b', and c' serve as place-holders for the change input test pattern. It will be understood by those skilled in the art that shadow Registers a', b', and c' should be
properly connected to ground to eliminate noise and leakage current. As shown, the outputs of shadow Registers a', b', and c' connect to the scan inputs of following Registers a, b, and c of scan chain register bank 201. As will be shown, in the delay
test operation, the shadow registers are utilized to hold the change input test pattern. In the normal operation (that is, when testing is not being performed and an IC of which combinational logic circuit 200 is a part is performing normal, ordinary,
non-test functions), the shadow registers a', b', and c' remain inactive. That is, the shadow Registers a', b', and c' are only activated when a testing signal indicates testing is desired. Reference material related to testing signals and other
general background material may be located in M. Abramovici, et al., Digital Testing and Testable Design Textbook, (1990), which is hereby incorporated by reference herein in its entirety.
As shown, shadow registers in FIGS. 2A, 2B, and 2C are labeled as Registers a', b', and c'. It is desired to apply the first test pattern sequence of ABC=<initialization test pattern of "010", change input test pattern of "110">, which was
discussed in relation to FIGS. 1A, 1B, and 1C wherein it was demonstrated that subsequent to initialization test pattern "010" being loaded, there was no practicable way to follow initialization test pattern "010" with change input test pattern "110" due
to the fact that in the absence of the present invention the number and type of scan chain test pattern sets which may be practicably applied to a particular combinational logic circuit are severely constrained by the arrangement of inputs to the
combinational logic circuit under test and the fact that the test patterns are sequentially scanned into scan chain register 101. The embodiment shown in FIGS. 2A, 2B, and 2C alleviates the foregoing noted constraints and makes it possible to
practicably apply virtually any imaginable test pattern set.
Referring now to FIG. 2B, shown is that initialization test pattern "010" and change output test pattern "110" have been alternately clocked in such that shadowed scan chain register bank 201 now contains contents of the sequence
A'AB'BC'C=<101100> (where A, A', B, B', C, C' refer to the respective components of initialization test pattern ABC="010" and change input test pattern A'B'C'="110" as depicted in FIG. 2A). As shown, in the current clock cycle, initialization test
pattern "010" is held in Registers a, b, and c.
With reference now to FIG. 2C, depicted is that on the next clock cycle rising edge, the logic value A' is shifted into Register a, the logic value B' is shifted into Register b, and the logic value C' is shifted into Register c. Thus, the
embodiment shown gives the ability to apply change input test pattern "110", subsequent to the application of initialization test pattern "010" in just one clock cycle. Thus, the embodiment shown allows the use of test pattern sequence
ABC=<initialization test pattern of "010", change input test pattern of "110">, to control the inputs to combinational logic circuit 200 such that the time delay on path 102, 104, 106 can be measured--something not possible under the related art,
as was explained above.
Those skilled in the art will recognize that the embodiment shown will allow the sequential application of any initialization test pattern-change input test pattern sets appropriate to combinational logic circuit 200. For example, as an
additional embodiment, those skilled in the art will recognize that the test pattern set of ABC=<initialization test pattern "110", and change input test pattern "010">, can also be achieved using the embodiment shown in FIG. 2A by applying the
data set A'AB'BC'C=<011100> in a fashion substantially similar to that just described in relation to FIGS. 2A and 2B.
The above examples show how the delay of path 102, 104, 106 can be tested using shadow registers. Those skilled in the art will appreciate that the shadow registers can be inserted for any arbitrary path, and that the embodiments shown and
discussed in relation to FIGS. 2A, 2B, and 2C can be extended from more than two successive patterns by the insertion of more shadow registers in a fashion analogous to that shown in for shadow Registers a', b', and c'. Those skilled in the art will
recognize that Registers a', a, b', b, c', and c can be implemented utilizing any number of components well known to those within the art, such as virtually any memory elements allowing the sequential application of data (e.g., flop flops, latches, or
random access memory sequentially employed) to appropriate inputs of any particular combinational logic circuit under test.
The embodiments illustrated with the help of FIGS. 2A, 2B, and 2C assumed that additional shadow registers would be inserted in addition to those registers normally utilized for the operation of an IC. However, other embodiments exist which will
provide essentially the same functionality of the embodiments shown in relation to FIG. 2, but without requiring any additional registers beyond those already present in an IC.
Referring now to FIGS. 3A, 3B, 3C, 3D, and 3E shown is a partially schematic diagram which will be utilized to illustrate embodiments of the present invention which will provide the advantage of the embodiments of FIGS. 2A, 2B, and 2C, but which
utilize pre-existing IC registers to provide the functions of shadow Registers a', b', and c'. Shown in FIG. | | |
