An output stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple input registers which hold input addresses and input data words; and a multiplexer circuit, having a plurality of parallel data inputs which concurrently receive the input addresses and the input data words, having control inputs for receiving a sequence of control signals, and which generates serial bit streams by selectively passing bits from the input addresses and input data words in response to the control signals. These serial bit streams from the multiplexer circuit preferably include a first bit stream which defines a data input to an integrated circuit chip that is to be tested, and a second bit stream which defines an expected output from the chip corresponding to the first bit stream. In one particular embodiment, the output stage further includes a memory address generator which generates a sequence of memory addresses, and a memory which receives the sequence of memory addresses, and in response, sends the sequence of control signals from a memory output to the control inputs of the multiplexer circuit. With this embodiment, the memory address generator can include a page register and a counter which together generate the sequence of memory addresses as multiple sub-sequences within respective pages; and the sub-sequences can be generated continuously with no gaps between them so that the serial bit streams from the multiplexer circuit will be generated continuously with no gaps between the serial bits.
RELATED CASES
The present invention, as identified by the above docket number and title, is related to four other inventions. Patent applications on all of these inventions were filed concurrently on Nov. 1999; and they have one common Detailed Description. These four related inventions are identified as follows: 1. Entitled "SYSTEM FOR TESTING IC CHIPS SELECTIVELY WITH STORED OR INTERNALLY GENERATED BIT STREAMS" having U.S. Ser. NO. 09/432,966; 2. Entitled "MULTI-STAGE ALGORITHMIC PATTERN GENERATOR FOR TESTING IC CHIPS" having U.S. Ser. No. 09/432,965; 3. Entitled "INITIAL STAGE OF A MULTI-STAGE ALGORITHMIC PATTERN GENERATOR FOR TESTING IC CHIPS" having U.S. Ser. No. 09/432,969; and 4. Entitled "INTERMEDIATE STAGE OF A MULTI-STAGE ALGORITHMIC PATTERN GENERATOR FOR TESTING IC CHIPS" having U.S. Ser. No. 09/432,968.
A circuit for generating one or more serial bit streams includes a memory coupled to a reformatter, which is in turn coupled to a serializer for converting parallel data to serial data. The memory includes a plurality of words having a known bit width (e.g., 32 bits) for storing one or more serial bit streams. The length of each serial bit stream is generally not an integer multiple of the memory's bit width, causing the last word storing each serial bit stream to contain a gap. The reformatter eliminates each such gap by combining bits from the last word of a bit stream with bits from the first word to provide a completely filled word to the serializer. As operation proceeds, the reformatter continues to combine bits from successive words to ensure that completely filled words are produced. Gaps that formerly appeared when producing serial bit streams are thereby eliminated.
