A semiconductor memory device having a circuit precharging a data line comprises a first precharge circuit, which precharges a first data line pair to a first voltage level in a precharge operation state, and a second precharge circuit, which precharges a second data line pair to a second voltage level in a precharge operation state. The semiconductor memory device comprises a data input driver, which receives data and drives the data to the first data line pair, a switch, which in response to a selection signal, connects or disconnects the first data line pair with the second data line pair, and a charge-sharing control circuit, which in response to the selection signal makes one line of the first data line pair and one line of the second data line pair share charge. The semiconductor memory device reduces current consumption over repeated write/precharge operations.

Provided is a bitline isolation circuit in a sense amplifier generating an isolation signal for controlling an isolation circuit to isolate a connection between a bitline sense amplifier and a bitline at the beginning of sensing of a read operation, according to an output of a control unit generating an isolation control signal, a start signal of the bitline sense amplifier, and a memory block select signal. The control unit includes: a write pulse generation unit for generating a first control signal, according to a first input signal as a bank address signal latched for every clock, a second input signal generated when a write or a read command is inputted, and a third input signal having a different level according to the read or the write command; and an isolation control signal generation unit for generating the isolation control signal, according to the first control signal and the second control signal having a different level according to a row active operation and a precharge operation.

There is provided a semiconductor memory device capable of performing high-speed reading even when the current capability of memory cells and transistors for charging is decreased, and a bit line capacitance is increased. In a sense amplifier, in addition to a P-type MOS transistor for charging, a P-type MOS transistor and a N-type MOS transistor are provided as a circuit for charging a selected bit line up to a switching level of a determination inverter included in a circuit for determining data of a memory cell, and a bit line is charged at high speed, whereby a read time is shortened.

There is provided a semiconductor memory device capable of performing high-speed reading even when the current capability of memory cells and transistors for charging is decreased, and a bit line capacitance is increased. In a sense amplifier, in addition to a P-type MOS transistor for charging, a P-type MOS transistor and a N-type MOS transistor are provided as a circuit for charging a selected bit line up to a switching level of a determination inverter included in a circuit for determining data of a memory cell, and a bit line is charged at high speed, whereby a read time is shortened.

A local input/output line precharge circuit of a semiconductor memory device comprises a precharge control unit, an equalization unit and a data output unit. The precharge control unit outputs a precharge control signal to precharge a pair of local input/output lines in response to a continuous write signal activated when a write operation continues. The equalization unit precharges and equalizing the pair of local input/output lines in response to the precharge control signal. The data output unit outputs data signals of a pair of global input/output lines to the pair of local input/output lines in response to output signal from the equalization unit. In the circuit, a local input/output line precharge operation is not performed at a continuous write mode, thereby reducing current consumption.