A messaging scheme that accomplishes cache-coherent data transfers during a memory read operation in a multiprocessing computer system is described. A source processing node sends a read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. In response to the read command, the target processing node transmits a probe command to all the remaining processing nodes in the computer system regardless of whether one or more of the remaining nodes have a copy of the data cached in their respective cache memories. Probe command causes each node to maintain cache coherency by appropriately changing the state of the cache block containing the requested data and by causing the node having an updated copy of the cache block to send the cache block to the source node. Each processing node that receives a probe command sends, in return, a probe response indicating whether that processing node has a cached copy of the data and the state of the cached copy if the responding node has the cached copy. The target node sends a read response including the requested data to the source node. The source node waits for responses from the target node and from each of the remaining node in the system and acknowledges the receipt of requested data by sending a source done response to the target node.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to the following patent applications: Ser. No. 09/217,367 filed Dec. 21, 1998; Ser. No. 09/217,649 filed Dec. 21, 1998, now U.S. Pat. No. 6,275,905; Ser. No. 09/217,699 filed Dec. 21, 1998, now U.S. Pat. No. 6,370,621; and Ser. No. 09/220,487 filed Dec. 23, 1998, now U.S. Pat. No. 6,167,492.
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for improving the accuracy of information available to a cache coherence controller are provided in order to allow the cache coherence controller to reduce the number of transactions in a multiple cluster system. Cache state information is provided to a home cluster cache coherence controller to allow silent evictions of shared memory lines and change to dirty associated intervening requests to be efficiently handled.
A disk drive backplane is described which includes a connector for interfacing with a corresponding connector on each of a plurality of carrier types. A plurality of status indicator arrays is provided, each of which corresponds to at least one of the carrier types and is operable to transmit status information. Each of the arrays is positioned to interface with a corresponding status interface on the corresponding carrier type(s). Circuitry is provided which enables one of the status indicator arrays thereby configuring the backplane to interface with a particular one of the carrier types.
Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is associated with each cache coherence controller identifying memory lines associated with the local cluster that are cached in remote clusters. Techniques are provided for managing eviction of entries in the cache coherence directory by locking memory lines in a home cluster without causing a memory controller to generate probes to processors in the home cluster.
According to the present invention, methods and apparatus are provided for static and dynamic power management of computer systems. A power authority manages power usage levels in computer systems by monitoring power consumption levels and providing power consumption information to the various systems. In one example, the power authority updates power tables to vary aggregate power consumption levels.
