A transmission type display includes a thin film transistor for driving a pixel electrode, which transistor is provided on a substrate, and a conductive shield layer provided at a position over the thin film transistor and under the pixel electrode. A first planarization film is formed to bury an irregular contour of the thin film transistor and the shield layer is disposed on the planarized surface of the first planarization film, and a second planarization film is formed to bury steps of the shield layer, and the pixel electrode is disposed on the planarized surface of the second planarization film. Since the transmission type display has the structure in which the conductive shield layer is put between the upper second planarization film and the lower first planarization film each of which is made from an insulating material, the shielding performance and the alignment characteristic of the display can be improved.
An active-matrix substrate is provided, which suppresses the unevenness of its surface due to the height difference of the TFTs and gate and data lines from the remaining area. After TFTs, gate lines, and data lines are formed on a transparent base, a transparent dielectric layer is formed on the base to cover the TFTs, the gate lines, and the data lines. The dielectric layer is selectively etched to form transparent dielectric portions arranged in a matrix array in such a way as to form a first plurality of recesses extending along the respective gate lines and a second plurality of recesses extending along the respective data lines. Each of the portions has a thickness equal to or greater than the maximum height of the TFTs, the gate lines, or the data lines, and a distance equal to or greater than the thickness thereof from a corresponding one of the TFTs, the gate lines, or the data lines. A planarization layer is then formed to fill at least the first plurality of recesses and the second plurality of recesses. Pixel electrodes are arranged on or over the flat surfaces of the respective portions. The connection part of each pixel electrode is connected to a corresponding one of the TFTs by way of a corresponding one of holes of the planarization layer.
A structure for preventing deteriorations of a light-emitting device and retaining sufficient capacitor elements' (condenser) required by each pixel is provided. A first passivation film, a second metal layer, a flattening film, a barrier film, and a third metal layer are stacked in this order over a transistor. A side face of a first opening provided with the flattening film is covered by the barrier film, a second opening is formed inside the first opening, and a third metal layer is connected to a semiconductor via the first opening and the second opening. A capacitor element that is formed of a lamination of a semiconductor of a transistor, a gate insulating film, a gate electrode, the first passivation film, and the second metal layer is provided.
An active-matrix substrate is provided, which suppresses the unevenness of its surface due to the height difference of the TFTs and gate and data lines from the remaining area. After TFTS, gate lines, and data lines are formed on a transparent base, a transparent dielectric layer is formed on the base to cover the TFTs, the gate lines, and the data lines. The dielectric layer is selectively etched to form transparent dielectric portions arranged in a matrix array in such a way as to form a first plurality of recesses extending along the respective gate lines and a second plurality of recesses extending along the respective data lines. Each of the portions has a thickness equal to or greater than the maximum height of the TFTs, the gate lines, or the data lines, and a distance equal to or greater than the thickness thereof from a corresponding one of the TFTs, the gate lines, or the data lines. A planarization layer is then formed to fill at least the first plurality of recesses and the second plurality of recesses. Pixel electrodes are arranged on or over the flat surfaces of the respective portions. The connection part of each pixel electrode is connected to a corresponding one of the TFTs by way of a corresponding one of holes of the planarization layer.
