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Claims  |
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What is claimed is:
1. A virtual channel memory access controlling circuit for controlling
accesses from a plurality of memory masters to a virtual channel memory
having a plurality of channels, comprising:
a channel information storing portion having a plurality of storage areas,
each of said storage areas being assigned to any of said memory masters,
each of said storage areas corresponding to each of said channels, each of
said storage areas having a channel number and a memory address, said
channel number identifying a channel, and said memory address being sent
to said virtual channel memory;
detecting means for detecting necessity of a change of assignment of
storage area between said memory masters;
changing means for dynamically changing the assignment of the storage area
between said memory masters; and
a plurality of idle counters, each of which corresponds to each of said
memory masters, for increasing an idle count when the corresponding memory
master is in an idle state and for clearing the idle count, when the
corresponding memory master accesses said virtual channel memory, wherein
the idle count is used as information for determining whether or not the
corresponding memory master has not accessed said virtual channel memory
for a predetermined time.
2. The virtual channel memory access controlling circuit as set forth in
claim 1, further comprising:
a memory master entry portion for enqueuing an identifier of a memory
master corresponding to the idle counter concerned with the idle count
reaching the predetermined value to a queue, when an idle count of any of
said idle counters reaches a predetermined value; and
a move channel controlling portion as said first memory master, a master
which is identified by said identifier at the top of said queue, and
designating, as one or more candidates for said storage area concerned
with the change of the assignment, one or more storage areas which are
assigned to said designated memory master, when an assignment of any
storage area should be changed from a first memory master to a second
memory master, for designating.
3. The virtual channel memory access controlling circuit as set forth in
claim 2, further comprising:
a plurality of LRU controlling portions, each of which corresponds to each
of said memory masters, for managing, in LRU system, one or more
identifiers of one or more storage areas which have been used for a
corresponding memory master to access to said memory master,
wherein said move channel controlling portion references identifiers of
storage areas managed by said LRU controlling portion for deciding which
of storage areas assigned to said first memory master is a target of
change of assignment.
4. The virtual channel memory access controlling circuit as set forth in
claim 3,
wherein if said first memory master is the same as said second memory
master, LRU information managed by said LRU managing portion is changed,
and change of assignment of a storage area between memory masters is not
performed.
5. The virtual channel memory access controlling circuit as set forth in
claim 2, further comprising:
a plurality of access counters, each of which corresponds to each of said
memory masters, for increasing an access count when a corresponding memory
master accesses said virtual memory and for clearing the access count when
a the corresponding idle counter is increased, said access count being
used as information that represents frequency of accesses from the
corresponding memory master to said virtual channel memory,
wherein when said queue stores no identifier, said move channel controlling
portion designates, as said first memory master, a memory master which
corresponds to an access counter of which the access count is minimum.
6. The virtual channel memory access controlling circuit as set forth in
claim 5,
wherein if there are a plurality of access counters whose access counts are
the minimum, said move channel controlling portion designates, as said
first memory master, a memory master among masters which correspond to the
plurality of access counters whose access counters are the minimum in
accordance with a predetermined priority.
7. The virtual channel memory access controlling circuit as set forth in
claim 2,
wherein said memory master entry portion deletes an identifier of the
memory master which is designated as said first memory master from said
queue.
8. The virtual channel memory access controlling circuit as set forth in
claim 2,
wherein said detecting means detects the necessity of change of assignment
of a storage area between memory masters when a channel miss takes place
for any memory master, and
wherein the second memory master is a memory master for which the channel
miss takes place.
9. A virtual channel memory access controlling circuit for controlling
accesses from a plurality of memory masters to a virtual channel memory
having a plurality of channels, comprising:
a channel information storing portion having a plurality of storage areas,
each of said storage areas being assigned to any of said memory masters,
each of said storage areas corresponding to each of said channels, each of
said storage areas having a memory address to be sent to said virtual
channel memory;
means for generating channel numbers, each of which identifies a channel
which corresponds to each of said storage areas;
detecting means for detecting necessity of a change of assignment of
storage area between said memory masters;
changing means for dynamically changing the assignment of the storage area
between said memory masters; and
a plurality of idle counters, each of which corresponds to each of said
respective memory masters, for increasing an idle count when the
corresponding memory master is in an idle state and for clearing the idle
count when the corresponding memory master accesses said virtual channel
memory,
wherein the idle count is used as information for determining whether or
not the corresponding memory master has not accessed said virtual channel
memory for a predetermined time.
10. The virtual channel memory access controlling circuit as set forth in
claim 9, further comprising:
a memory master entry portion for enqueuing an identifier of a memory
master corresponding to the idle counter concerned with the idle count
reaching the predetermined value to a queue, when an idle count of any of
said idle counters reaches a predetermined value; and
a move channel controlling portion for designating, as said first memory
master, a master which is identified by said identifier at the top of said
queue, and designating, as one or more candidates for said storage area
concerned with the change of the assignment, one or more storage areas
which are assigned to said designated memory master, when an assignment of
any storage area should be changed from a first memory master to a second
memory master.
11. The virtual channel memory access controlling circuit as set forth in
claim 10, further comprising:
a plurality of LRU controlling portions, each of which corresponds to each
of said memory masters, for managing, in LRU system, one or more
identifiers of one or more storage areas which have been used for a
corresponding memory master to access to said memory master,
wherein said move channel controlling portion references identifiers of
storage areas managed by said LRU controlling portion for deciding which
of storage areas assigned to said first memory master is a target of
change of assignment.
12. The virtual channel memory access controlling circuit as set forth in
claim 11,
wherein if said first memory master is the same as said second memory
master, LRU information managed by said LRU managing portion is changed,
and change of assignment of a storage area between memory masters is not
performed.
13. The virtual channel memory access controlling circuit as set forth in
claim 10, further comprising:
a plurality of access counters, each of which corresponds to each of said
memory masters, for increasing an access count when a corresponding memory
master accesses said virtual memory and for clearing the access count when
a the corresponding idle counter is increased, said access count being
used as information that represents frequency of accesses from the
corresponding memory master to said virtual channel memory,
wherein when said queue stores no identifier, said move channel controlling
portion designates, as said first memory master, a memory master which
corresponds to an access counter of which the access count is minimum.
14. The virtual channel memory access controlling circuit as set forth in
claim 13,
wherein if there are a plurality of access counters whose access counts are
the minimum, said move channel controlling portion designates, as said
first memory master, a memory master among masters which correspond to the
plurality of access counters whose access counters are the minimum in
accordance with a predetermined priority.
15. The virtual channel memory access controlling circuit as set forth in
claim 10,
wherein said memory master entry portion deletes an identifier of the
memory master which is designated as said first memory master from said
queue.
16. The virtual channel memory access controlling circuit as set forth in
claim 10,
wherein said detecting means detects the necessity of change of assignment
of a storage area between memory masters when a channel miss takes place
for any memory master, and
wherein the second memory master is a memory master for which the channel
miss takes place. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a virtual channel memory access
controlling circuit and in particular, to a virtual channel memory access
controlling circuit for controlling a virtual channel memory (referred to
as VCM) with a controlling method of the least recently used method
(referred to as LRU).
2. Description of the Prior Art
Next, with reference to the accompanying drawings, a conventional VCM will
be described. FIG. 1 is a schematic diagram showing the concept of the
VCM. FIG. 2 is a block diagram showing the structure of a conventional
memory system using the VCM. Referring to FIG. 1, VCM 60 has a plurality
of channels 50 composed of registers, and a memory cell 51 is composed of
a plurality of segments. Each of the channels 50 is connected to all the
segments of the memory cell 51. Each segment is a data access unit. In
other words, any address of the memory cell 51 can be accessed through any
channel. Each of the channels 50 is assigned a unique channel number.
Referring to FIG. 2, the memory system is composed of VCM 60, virtual
channel memory access controlling circuit 62, and memory masters 67, 70,
and 73. The memory masters 67, 70, and 73 are processors that execute, for
example, jobs.
The virtual channel memory access controlling circuit 62 performs
reading/writing operations, i.e. foreground process, from/to the channels
50. The virtual channel memory access controlling circuit 62 also performs
internal operations such as a data transferring operation between the
memory cell 51 and the channels 50, a pre-charging operation, and a
refreshing operation for the memory cell 51, i.e. background process,
independent from the foreground process. Since the virtual channel memory
access controlling circuit 62 independently performs the foreground
process and the background process, a high average data transfer rate for
the VCM 60 can be accomplished.
The channels 50 of the VCM 60 and the virtual channel memory access
controlling circuit 62 are connected by a dedicated memory bus 61. The
virtual channel memory access controlling circuit 62 comprises a memory
interface controlling portion 63, an arbiter portion 64, channel
information storing portions 65, 68, and 71, and LRU controlling portions
66, 69, and 72. The memory interface controlling portion 63 controls the
memory bus 61. The arbiter portion 64 arbitrates access requests issued
from the memory masters 67, 70, and 73. The channel information storing
portions 65, 68, and 71 store information of the channels 50 of the VCM
60. The LRU controlling portions 66, 69, and 72 control the channel
information storing portions 65, 68, and 71 corresponding to the LRU
controlling method.
The channel information storing portions 65, 68, and 71 and the LRU
controlling portions 66, 69, and 72 are disposed corresponding to the
memory masters 67, 70, and 73, respectively, so as to fulfill the feature
of the VCM 60. To deal with multitask processes of the memory masters 67,
70, and 73, proper numbers of channels 50 are assigned to the memory
masters 67, 70, and 73 so as to shorten the access wait times of the
memory masters 67, 70, and 73. In that example, as shown in FIG. 2, it is
assumed that three channels 50 are assigned to the memory master 67; two
channels 50 are assigned to the memory master 70; and four channels 50 are
assigned to the memory master 73. In that case, the channels 50 are not
redundantly assigned to a plurality of memory masters. Thus, the number of
channels 50 is nine.
Next, the operation of the above-described virtual channel memory access
controlling circuit 62 will be described. In the example, it is assumed
that the memory master 67 reads data from the VCM 60.
When the memory master 67 issues a read request to the arbiter portion 64,
the arbiter portion 64 arbitrates the read request issued from the memory
master 67 with access requests issued from the memory masters 70 and 73 to
the VCM 60. The arbiter portion 64 permits the read request of the memory
master 67 just after or in a predetermined time period after the memory
master 67 has issued the read request. Thereafter, the memory master 67
designates a memory address that contains a bank address, a row address, a
segment address, and a column address, and issues the read request with
the designated address to the channel information storing portion 65.
The channel information storing portion 65 determines whether the bank
address, the row address, and the segment address in the memory address of
the read request match those in any storage area of the channel
information storing portion 65. When the determined result is Yes, a
channel hit takes place. When the determined result is No, a channel miss
takes place. Each register of each channel 50 stores data of address
groups designated by a bank address, a row address, and a segment address.
When a channel hit takes place, the memory address supplied from the memory
master 67 to the channel information storing portion 65 is stored to a
storage area corresponding to the hit channel. The LRU controlling portion
66 designates the hit channel as the lowest rank channel. In other words,
the LRU controlling portion 66 designates the hit channel as the most
recently used channel. In addition, the LRU controlling portion 66
upwardly shifts the ranks of the other channels by one.
On the other hand, when a channel miss takes place, the memory address
supplied from the memory master 67 to the channel information storing
portion 65 is stored to a storage area of the highest rank channel. In
addition, the LRU controlling portion 66 shifts the channel that has
stored the memory address from the highest rank channel to the lowest rank
channel. In other words, the LRU controlling portion 66 designates a
channel to which a memory address is newly stored as a channel that was
most recently used. In addition, the LRU controlling portion 66 upwardly
shifts the ranks of the other channels by one.
The channel information storing portion 65 outputs a memory address stored
in the storage area to the memory interface controlling portion 63 along
with channel information. As a result, the memory interface controlling
portion 63 generates a read cycle on the memory bus 61.
FIG. 3 is a time chart showing the cases that a channel hit and a channel
miss take place in a read cycle.
Referring to FIG. 3, PRE represents a pre-charge command that sends a bank
address; ACT represents an activate command that sends a bank address and
a row address; PFC is a pre-fetch command that sends a segment address and
a channel number; and READ represents a read command that sends a channel
number and a column address. When a channel miss takes place, namely,
valid data to be read is stored in none of channels 50, a bank that has
been activated in the memory cell 51 is deactivated by a pre-charge
command. Then, a row address at which valid data is stored is activated by
an activate command. Then, the data is copied from the memory cell 51 to
the channel 50 by a pre-fetch command. Then, the data is read from the
channel 50 by a read command. On the other hand, in the case of a hit
cycle, namely, data to be read is stored in a channel 50, the cycle is
completed with only a read command. As is clear from FIG. 3, the cycle
time in the case of a channel miss takes place is longer than that in the
case of a channel hit.
A prior art reference of JPA 7-221797 discloses a FIFO memory controlling
system. The FIFO memory controlling system can be used in common with an
information processing system having one channel of an information
generating source that generates information at a high data generation
frequency and another information processing having a plurality of
channels of information generating sources that generate information at a
low data generation frequency. In addition, the memory use efficiency of
the FIFO memory controlling system is high.
However, the above-described prior art references have the following
problems. The number of channels assigned to each of the memory masters
67, 70, and 73 is designated by a setup register such as a configuration
register. The number of channels that have been assigned cannot be changed
unless the system is reset. Thus, it is very difficult to automatically
detect the memory access frequencies of the memory masters 67, 70, and 73
and adjust the number of channels assigned to each of the memory masters
67, 70, and 73.
For example, in FIG. 2, it is assumed that the memory access frequency of
the memory master 70 is very high, whereas the memory access frequency of
the memory master 73 is very low. In contrast with this, the number of
channels assigned to the memory master 70 is as small as "2", whereas the
number of channels assigned to the memory master 73 is as large as "4".
When the number of channels assigned is small, the probability that a
channel miss that occupies the memory bus 61 takes place is high. When the
memory access frequency is high, the probability becomes much higher. As a
result, the performance of the system deteriorates.
According to the prior art reference of JPA 7-221797, only a combination of
segments of the FIFO is changed. Thus, the number of combinations is
limited.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a system that uses a VCM
with the LRU controlling method that allows channels to be moved among
memory masters and automatically assigned thereto in consideration of the
access frequency, so that the use efficiency of channels of the VCM is
improved, and the memory access performance is improved.
According to a first aspect of the present invention, there is provided a
virtual channel memory access controlling circuit for controlling accesses
from a plurality of memory masters to a virtual channel memory having a
plurality of channels, comprising: a channel information storing portion
having a plurality of storage areas, each of the each storage areas being
assigned to any of the memory masters, each of the storage areas
corresponding to each of the channels, each of the storage areas having a
channel number and a memory address, the channel number identifying a
channel, the memory address being sent to the virtual channel memory;
detecting means for detecting necessity of a change of assignment of
storage area between memory masters; and changing means for dynamically
changing the assignment of the storage area between memory masters.
According to a second aspect of the present invention, there is provided a
virtual channel memory access controlling circuit for controlling accesses
from a plurality of memory masters to a virtual channel memory having a
plurality of channels, comprising: a channel information storing portion
having a plurality of storage areas, each of the each storage areas being
assigned to any of the memory masters, each of the storage areas
corresponding to each of the channels, each of the storage areas having a
memory address to be sent to the virtual channel memory; means for
generating channel numbers, each of which identifies a channel which
corresponds to each of the storage areas; detecting means for detecting
necessity of a change of assignment of storage area between memory
masters; and changing means for dynamically changing the assignment of the
storage area between memory masters.
The virtual channel memory access controlling circuit according to the
first and second aspects may further comprise: a plurality of idle
counters, each of which corresponds to each of the respective memory
masters, for increasing an idle count when the corresponding memory master
is in an idle state and for clearing the idle count when the corresponding
memory master accesses the virtual channel memory, wherein the idle count
is used as information for determining whether or not the corresponding
memory master has not accessed the virtual channel memory for a
predetermined time.
The virtual channel memory access controlling circuit according to the
first and second aspects may further comprise: a memory master entry
portion, when an idle count of any of the idle counters reaches a
predetermined value, for enqueuing an identifier of a memory master
corresponding to the idle counter concerned with the idle count reaching
the predetermined value to a queue; and a move channel controlling
portion, when an assignment of any storage area should be changed from a
first memory master to a second memory master, for designating, as the
first memory master, a master which is identified by the identifier at the
top of the queue, and designating, as one or more candidates for the
storage area concerned with the change of the assignment, one or more
storage areas which are assigned to the designated memory master.
The virtual channel memory access controlling circuit according to the
first and second aspects may further comprise: a plurality of LRU
controlling portions, each of which corresponds to each of the memory
masters, for managing, in LRU system, one or more identifiers of one or
more storage areas which have been used for a corresponding memory master
to access to the memory master, wherein the move channel controlling
portion references identifiers of storage areas managed by the LRU
controlling portion for deciding which of storage areas assigned to the
first memory master is a target of change of assignment.
The virtual channel memory access controlling circuit according to the
first and second aspects may further comprise: a plurality of access
counters, each of which corresponds to each of the memory masters, for
increasing an access count when a corresponding memory master accesses the
virtual memory and for clearing the access count when a the corresponding
idle counter is increased, the access count being used as information that
represents frequency of accesses from the corresponding memory master to
the virtual channel memory, wherein when the queue stores no identifier,
the move channel controlling portion designates, as the first memory
master, a memory master which corresponds to an access counter of which
the access count is minimum.
In the virtual channel memory access controlling circuit according to the
first and second aspects, the memory master entry portion may delete an
identifier of the memory master which is designated as the first memory
master from the queue.
In the virtual channel memory access controlling circuit according to the
first and second aspects, the detecting means may detects the necessity of
change of assignment of a storage area between memory masters when a
channel miss takes place for any memory master, and the second memory
master may be a memory master for which the channel miss takes place.
In the virtual channel memory access controlling circuit according to the
first and second aspects, if the first memory master is the same as the
second memory master, LRU information managed by the LRU managing portion
may be changed, and change of assignment of a storage area between memory
masters may not be performed.
In the virtual channel memory access controlling circuit according to the
first and second aspects, if there are a plurality of access counters
whose access counts are the minimum, the move channel controlling portion
may designate, as the first memory master, a memory master among masters
which correspond to the plurality of access counters whose access counters
are the minimum in accordance with a predetermined priority.
These and other objects, features and advantages of the present invention
will become more apparent in light of the following detailed description
of the best mode embodiment thereof, as illustrated in the accompanying
drawings.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a block diagram showing the concept of a VCM;
FIG. 2 is a block diagram showing the structure of a memory system using a
conventional VCM;
FIG. 3 is a time chart showing an access to the VCM;
FIG. 4 is a block diagram shows the structure of an embodiment of the
present invention;
FIG. 5 is a schematic diagram for explaining channel information;
FIGS. 6A and 6B are a schematic diagrams for explaining assignments of
channel information storing areas;
FIG. 7 is a flow chart showing the operation of an idle counter shown in
FIG. 4;
FIG. 8 is a flow chart showing the operation of an access counter shown in
FIG. 4;
FIG. 9 is a flow chart showing the operation of a memory master entry
portion shown in FIG. 4;
FIG. 10 is a flow chart showing the operation of a moving channel
controlling portion shown in FIG. 4;
FIG. 11 is a first time chart showing the operation of the embodiment of
the present invention;
FIG. 12 is a second time chart showing the operation of the embodiment of
the present invention;
FIG. 13 is a third time chart showing the operation of the embodiment of
the present invention; and
FIG. 14 is a fourth time chart showing the operation of the embodiment of
the present invention.
DESCRIPTION OF PREFERRED EMBODIMENTS
Next, with reference to the accompanying drawings, a first embodiment of
the present invention will be described.
FIG. 4 is a block diagram showing the structure of the first embodiment of
the present invention. Referring to FIG. 4, the first embodiment of the
present invention comprises a plurality of memory masters 10, 11, and 12,
a VCM 29, a virtual channel memory access controlling circuit 90, and a
memory bus 80. Each of the memory masters 10, 11, and 12 issue access
requests to the VCM 29. The memory bus 80 connects the VCM 29 and the
virtual channel memory access controlling circuit 90.
The virtual channel memory access controlling circuit 90 comprises a
channel information storing portion 13, an LRU controlling portion 16, an
LRU controlling portion 17, and an LRU controlling portion 18. The channel
information storing portion 13 stores a bank address, a row address, a
column address, a segment address, and a channel number (these information
is referred to as channel information as a whole) of a cycle generated by
each of the memory masters 10, 11, and 12. The LRU controlling portion 16
corresponds to the memory master 10. The LRU controlling portion 17
corresponds to the memory master 11. The LRU controlling portion 18
corresponds to the memory master 12. The LRU controlling portions 16, 17,
and 18 control channel information based on the LRU method.
The virtual channel memory access controlling circuit 90 also comprises
idle counters 19, 20, and 21. When the memory master 10 is in an idle
state, the idle counter 19 is increased with a control clock (not shown).
When the memory master 10 issues an accesses request, the count of the
idle counter 19 is cleared. When the memory master 11 is in an idle state,
the idle counter 20 is increased with the control clock. When the memory
master 11 issues an accesses request, the count of the idle counter 20 is
cleared. When the memory master 12 is in an idle state, the idle counter
21 is increased with the control clock. When the memory master 12 issues
an accesses request, the count of the idle counter 21 is cleared.
The virtual channel memory access controlling circuit 90 further comprises
access counters 22, 23, and 24. When the memory master 10 issues an access
request, the access counter 22 is increased. When the count of the idle
counter 19 reaches a predetermined value, the count of the access counter
22 is cleared. When the memory master 11 issues an access request, the
access counter 23 is increased. When the count of the idle counter 20
reaches a predetermined value, the count of the access counter 23 is
cleared. When the memory master 12 issues an access request, the access
counter 23 is increased. When the count of the idle counter 21 reaches a
predetermined value, the count of the access counter 23 is cleared.
The virtual channel memory access controlling circuit 90 still further
comprises a memory master entry portion 25, a moving channel controlling
portion 26, an arbiter portion 27, and a memory interface controlling
portion 28. When the count of the idle counter 19, 20, or 21 reaches a
predetermined value, the memory master entry portion 25 enqueues an
identifier of the corresponding memory master 10, 11, or 12 to a queue
therein. In response to an occurrence of a channel miss, the moving
channel controlling portion 26 controls a change of an assignment of a
channel 50 to the memory master 10, 11, or 12 on the basis of information
of the access counters 22, 23, and 24 and information of the memory master
entry portion 25. The channel miss represents that the bank address, the
row address, and the segment address of an access request issued from a
memory master (the memory master 10, 11 or 12) matches none of the bank
addresses, the row addresses, and the segment addresses of channel
information stored in storage areas of the channel information storing
portion 13 which is assigned to the memory master (the memory masters 10,
11 or 12). The arbiter portion 27 arbitrates access requests issued from
the memory masters 10, 11, and 12. The memory interface controlling
portion 28 generates a cycle on the memory bus 80 corresponding to the
arbitrated result of the arbiter portion 27 and the address in the channel
information in the channel information storing portion 13.
The number of storage areas in the channel information storing portion 13
is the same as the number of the channels 50 in the VCM 29. Thus, each
storage area corresponds to each channels 50. Each storage area is
dynamically assigned to one of the memory masters 10, 11, and 12.
However, besides the memory masters 10, 11, and 12, other memory masters
(not shown) are connected. Thus, the virtual channel memory access
controlling circuit 90 also comprises LRU controlling portions, idle
counters, and access counters corresponding to those memory counters. For
easy understanding, the description of those portions is omitted.
As shown in FIG. 1, the VCM 29 comprises a plurality of channels 50 and a
memory cell 51. The memory cell 51 is composed of a plurality of segments.
The channels 50 are composed of for example registers. Each channel 50 is
connected to all the segments. Each channel 50 stores data for one
segment. Each segment is uniquely designated by a bank address, a row
address, and a segment address. Data of one segment that is read from the
memory cell 51 is held in one channel 50 until the data is rewritten in
read mode. In addition, data that is written from the virtual channel
memory access controlling circuit 90 is held in a channel 50 until the
data is rewritten in write mode.
As shown in FIG. 5, a memory address consists of a bank address (1 bit), a
row address (13 bits), a segment address (2 bits) that represents a
segment unit, and a column address (7 bits), for example. The channel
information consists of a memory address and a channel number. The memory
master 10, 11, and 12 sends the bank address, the row address, the segment
address, and the column address to each storage area of the channel
information storing portion 13.
All the channels 50 are assigned unique channel numbers. When there are
channels 50 as many as 16, each channel number is composed of 4 bits. The
channel information storing portion 13 has storage areas for identifying
the channels 50 assigned thereto. For example, referring to FIG. 6A, the
storage areas 0 to 2 of the channel information storing portion 13 stores
channel information of channels 50 corresponding to the memory master 10;
the storage areas 3 and 4 store channel information of channels 50
corresponding to the memory master 11; the storage areas 12 to 15 store
channel information of channels 50 corresponding to the memory master 12.
In this example, the channel numbers 0 to 15 correspond to the storage
areas 0 to 15, respectively.
When the system is initialized, the channel numbers 0 to 15 are generated
and stored as part of channel information in the storage areas 0 to 15,
respectively.
The storage areas 0 to 15 have respective valid flags (not shown). Each
valid flag represents whether or not channel information in the
corresponding storage area is valid. When the system is initialized, the
valid flags are reset. When channel information is stored to a storage
area, the relevant valid flag is set. When channel information is deleted
from a storage area, the relevant valid flag is reset again. Since the
operation of the valid flag is the same as that used in a normal caching
process, the description is omitted
FIG. 7 is a flow chart for explaining the operations of the idle counters
19, 20, and 21. Referring to FIG. 7, when a memory master (the memory
master 10, 11 or 12) is in an idle state (Yes at step S31), the
corresponding idle counter (the idle counter 19, 20 or 21) is increased
with the control clock (at step 34) until the count thereof becomes a
predetermined value (No at step S32). When the memory master (the memory
master 10, 11,or 12) is in the idle state (Yes at step S31), if the count
is the predetermined value (Yes at step S32), the count is held (at step
S35). On the other hand, when the memory master (the memory master 10, 11,
or 12) issues an access request (No at step S31) or when a channel moves
(Yes at step S36) takes place, the counts of the idle counter (the idle
counter 19, 20, or 21) is cleared (at step S33). As a result, it can be
determined whether or not the memory master has not issued an access
request for a long time.
FIG. 8 is a flow chart for explaining the operations the access counters
22, 23, and 24. Referring to FIG. 8, when a memory master (the memory
master 10, 11, or 12) issues an access request (Yes at step S43), if the
count of the corresponding counter (the access counter 22, 23, or 24) is
not a predetermined value (No at step S44), the access counter is
increased (at step S45). Otherwise (Yes at step S44), the count of the
access counter is held (at step S46). When the count of the corresponding
idle counter (the idle counter 19, 20, or 21) becomes a predetermined
value (Yes at step S41), the count of the access counter (the access
counter 22, 23, or 24) is cleared (at step S42).
FIG. 9 is a flow chart for explaining the operation of the memory master
entry portion 25. Referring to FIG. 9, when a count of an idle counter
(the idle counter 19, 20, or 21) becomes a predetermined value (Yes at
step S54), the memory master entry portion 25 enqueues an identifier of a
corresponding memory master (the memory master 10, 11, or 12) to a queue
therein (at step S55). Thus, when a channel move is required due to an
occurrence of a channel miss or the like, channel information on a channel
to be moved with priority can be obtained. In other words, a memory master
with the identifier that is placed at the beginning of the queue is a
memory master from which a channel is removed with a priority. When a
memory master (the memory master 10, 11, or 12) whose identifier has been
enqueued in the queue of the memory master entry portion 25 issues an
access request (Yes at step S51) or when a channel move takes place for
the memory master (Yes at step S53), the entry of the identifier of the
memory master is removed from the queue (at step S52). If a void entry
arises in the queue of the memory master entry portion 25 as a result of
the removal, the following entries are upwardly shifted by one.
FIG. 10 is a flow chart for explaining the operation of the moving channel
controlling portion 26. Referring to FIG. 10, when a channel 50 should be
moved from a master memory to another master memory due to an occurrence
of a channel miss or the like, the moving channel controlling portion 26
controls which channel assigned to which memory master should be
reassigned to the latter memory master on the basis of the counts of the
access counters 22, 23, and 24, the identifiers of the memory masters
enqueued in the queue of the memory master entry portion 25, and the LRU
information of the storage areas assigned to the memory masters managed by
the LRU controlling portion 16, 17, and 17.
When a channel move is required (Yes at step S61) due to, for example, a
channel miss, if the queue of the memory master entry portion 25 has at
least an entry of an identifier of a memory master (the memory master 10,
11, or 12) having a movable channel (Yes at step S62), the moving channel
control portion 26 designates the memory master (the memory master 10, 11,
or 12) whose identifier was enqueued earliest in the queue of the memory
master entry portion 25 and then designates the channel which is at the
highest rank in the corresponding LRU controlling portion (the LRU
controlling portion 16, 17, or 18) among one or more channels which are
assigned to the memory master (step 63).
When a channel move is required (Yes at step S61), if the memory master
entry portion 25 does not have an entry of an identifier of a memory
master (the memory master 10, 11, or 12) having a movable channel (No at
step S62), moving channel controlling portion 26 compares the counts of
the access counters 22 to 24 one another (at step S64). If the memory
master (the memory master 10, 11 or 12) which the count of the access
counter (the access counter 22, 23 or 24) corresponding to is the minimum
is the same as the memory master (the memory master 10, 11 or 12) for
which a channel miss has taken place (Yes at step S65), the moving channel
controlling portion 26 updates the corresponding LRU controlling portion
(the LRU controlling portion 16, 17 or 18) without performing a channel
move (at step S66). The updating the corresponding LRU controlling portion
comprises rewriting the bank address, the row address, the column address,
and the segment address written in an entry at the highest rank of the LRU
controlling portion to those that are input from the memory master,
placing the bank address, the row address, the column address, and the
segment address that are input from the memory master at the lowest rank,
and upwardly shifting the ranks of the other bank addresses, row
addresses, column addresses, and segment addresses upward.
If the memory master (the memory master 10, 11 or 12) which the count of
the access counter (the access counter 22, 23 or 24) corresponding to is
the minimum is the same as the memory master (the memory master 10, 11 or
12) for which a channel miss has taken place (No at step S65), the moving
channel controlling portion 26 determines whether or not the minimum count
is shared by two or more access counters among the access counters 22, 23,
and 24 (at step S67). If Yes at step S67, the moving channel controlling
portion 26 designates the memory master (the memory master 10, 11, or 12)
whose priority is the highest and then designates the channel which is at
the highest rank in the corresponding LRU controlling portion (the LRU
controlling portion 16, 17, or 18) among one or more channels which are
assigned to the memory master (step 68). Here, priorities of the memory
masters 10, 11, 12 have been determined beforehand. If No at step S67, the
moving channel controlling portion 26 designates the memory master (the
memory master 10, 11, or 12) which the count of the access counter
corresponding to is the minimum and then designates the channel which is
at the highest rank in the correspond | | |
