A write driver circuit includes a drive circuit having a first drive node adapted to receive a first voltage, a second drive node, an input adapted to receive a data signal, and an output. The drive circuit couples the output to the first voltage node when the data signal has a first logic voltage, and couples the output to the second drive node when the data signal has a second logic voltage. A test circuit has an input adapted to receive a test mode signal, and an output coupled to the second drive node. The test circuit develops a first impedance between the second drive node and a second voltage source when the test mode signal is active, and develops a second impedance between the second drive node and the second voltage source when the test mode signal is inactive.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a Continuation of U.S. patent application Ser. No. 09/024,826, filed Feb. 17, 1998 now U.S. Pat. No. 6,161,204.
