A method of testing and/or repairing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers shared by the arrays are selectively coupled by isolation transistors to the digit lines of respective columns in each array. The sense amplifiers and isolation transistors are controlled to sequentially writing known data bits to a plurality of rows in each of the arrays. The rows in the first and second arrays remain activated for a testing interval of sufficient duration to allow charge to transfer through any inter-cell defects between the cells in the activated rows and cells that are not in an activated row. Cells in each non-activated row are then read. Inter-cell defects may also be repaired by activating the rows in the first and second arrays in a manner that couples adjacent memory cells to digit lines having different complimentary voltages.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of U.S. patent application Ser. No. 09/047,760 now U.S. Pat. No. 6,167,541, filed Mar. 24, 1998.
A method for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. The method provides that either a temporary or permanent circuit "defect" is intentionally created in the physical layout. Then, the new electrical schematic is extracted from the modified physical layout. Subsequently, if the design "defect" which was created is temporary, the new electrical schematic is simulated, the logical address of the "defect" is determined, and the extracted logical address is compared to the expected address to verify the logical to physical correlation. Alternatively, if the design "defect" which was created is permanent, after the new electrical schematic is extracted from the modified physical layout, the product is fabricated and the known design "defect" location is used to correlate to the electrically-tested defect logical location.
A memory device has a number of memory segments connected to a supply source through a supply control circuit. If one of the memory segments is defective, the supply control circuit isolates the defective memory segment from the supply source. The memory device replaces the defective memory segment with a redundant segment.
