The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A "randomize" method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. If a constraint block of an instance is active or ON, then all the constraint expressions in the block will act to constrain their lhs random variable. A constraint block which is OFF means that all of its constraint expressions will not act to constrain their random variables. The method "constraint_mode" can be used to turn ON or OFF any constraint blocks of an instance.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to the following co-pending U.S. patent applications, all of which were filed on the same day as the present application and all of which are herein incorporated by reference: "Method and Apparatus For Random Stimulus Generation," filed with inventors Won Sub Kim, Mary Lynn Meyer and Daniel Marcos Chapiro, having McDermott, Will & Emery of and U.S. Patent Office Ser. No. 09/298,986; and "Method and Apparatus For Random Stimulus Generation," filed with inventors Won Sub Kim, Mary Lynn Meyer and Daniel Marcos Chapiro, having McDermott, Will & Emery of and U.S. Patent Office Ser. No. 09/298,981.
This application is related to the following co-pending U.S. patent application, all of which is herein incorporated by reference: "Method and Apparatus For Determining Expected Values During Circuit Design Verification," filed on Mar. 31, 1999, with inventors Won Sub Kim, Valeria Maria Bertacco, Daniel Marcos Chapiro and Sandro Pintz, having McDermott, Will & Emery of and U.S. Patent Office Ser. No. 09/283,774.
A system and method is provided for creating a digital circuit, such as a configured FPGA or a VLSI chip. User code includes algorithm specifications having precisely defined operators and variables, data representation specifications and data communication specifications. The user code is compiled to create a digital circuit. For example, the compiled user code is used to generate either a hard-wired digital circuit or the configuration instructions for configuring a re-configurable digital circuit.
A computer-aided circuit design application has a virtual node feature and a design tool. The virtual node feature is adapted to access design specification information in a first data format and to represent the accessed design specification information as a virtual data node object within a list of node objects in a second data format. The design tool is operable on the list of node objects and the virtual data node object.
