An electronic exposure control system for an active pixel CMOS image sensor includes a row decoder and a column decoder for respective row-wise and column-wise addressing of the image signal generating pixels. The decoders receive row and column addresses and control signals from a controller. The row addresses received by the row decoder are alternately switched between a predetermined row address for resetting the image signals of pixels in said row and another predetermined spaced apart row address for enabling the image signals of pixels in said selected row to be read out by the column decoder. By providing a predetermined sequence of row addresses, a "rolling shutter" can be created and/or the exposure time of the pixels can be selected to be different from the time to expose an entire frame. The image sensor can also be operated in an interlaced mode and/or specific areas on the image sensor can be selected to be reset and read out.
A system for inspecting components is provided. The system includes a CMOS imaging system generating image data, such as pixel data from a pixel array. An image analysis system is connected to the CMOS imaging system, the image analysis system receiving the image data and generating image analysis data. The CMOS imaging system generates the image data at a rate that allows the CMOS imaging device to be used for inspecting components.
An imaging array having a CCD imaging array that includes a plurality of pixels that accumulate charge when exposed to light and a readout amplifier is disclosed. The readout amplifier includes an operational amplifier having an input and an output port and a feedback capacitor connecting the input and output ports and a variable impedance path between the input and output ports, the path having an impedance controlled by a reset signal. A reset signal generator generates the reset signal in three sequential phases in which the path between the input and output ports has three impedance values to provide a starting voltage at the amplifier input prior to the measurement of charge from each pixel that has reduced noise.
In an X-Y address imaging device having an electronic shutter function, a vertical driving section includes a vertical scanning circuit and a vertical shutter scanning circuit. A horizontal driving section includes a horizontal scanning circuit and a horizontal shutter scanning circuit. The horizontal shutter scanning circuit selects, on a pixel basis, a pixel for which to perform a shutter operation from the pixels of a read pixel row selected by the vertical scanning section. After a lapse of an exposure time that is an integral multiple of a one-pixel selection period, a signal of the selected pixel is read out by scanning by the horizontal scanning circuit. This realizes an electronic shutter that enables not only an exposure time that is an integral multiple of 1H but also an exposure time having a time shorter than 1H as a unit.
A decoder apparatus for selecting column lines of a CMOS imager pixel array is disclosed. The decoder apparatus is made up of at least one first decoder and at least one set of second decoders, each set being associated with respective first decoder. The first decoder decodes a first portion of an address representing a desired pixel array column and, depending on the results of the first decoding operation, selectively enables the associated second decoder set which decodes a second portion of the address to select a column line.
A solid-state image pickup device comprises for each pixel a photoelectric converter PD, an input terminal FD of a signal amplifier and a transfer switch TX for transferring an optical signal from the photoelectric converter to the input terminal. The device additionally comprises means for resetting the photoelectric converter by opening the transfer switch TX under a condition of holding the voltage of the input terminal FD to a fixed high level before storing the optical signal in the photoelectric converter PD. With this arrangement, any residual electric charge in the photoelectric converter can be eliminated without paying the cost of reducing the manufacturing yield and degrading the chip performance.
