A two-way time transfer protocol includes: sending a signal from a first node including a first clock and a first time interval counter coupled to the first clock over a transport physical layer coupled to the first node to a second node coupled to the transport physical layer, the second node including a second clock and a second time interval counter coupled to the second clock; then sending a last second node time interval counter value from the second time interval counter of the second node over the transport physical layer to the first node; and then comparing at the first node a last first node time interval counter value to the last second node time interval counter value. A first-way path latency from the first node to the second node is substantially equal to a second-way path latency from the second node to the first node, and all of a first node transmit delay, a first node receive delay, a second node transmit delay and a second node receive delay are substantially constant.

An information-processing device for communicating with a communication device includes a RTT measurement unit configured to measure a round trip time between the information-processing device and the communication device, a RTT judgment unit configured to determine whether the round trip time exceeds a predetermined upper limit value, a unit-type information acquiring unit configured to acquire an identification of the communication device when the round trip time is not greater than the upper limit value, a limit value judgment unit configured to measure amount of cumulative information accumulated during content is transmitted to the communication device, a cumulative information storage unit configured to store the measured amount of cumulative information, and a cumulative information management unit configured to control to store the cumulative information in the cumulative information storage unit when the amount of cumulative information exceeds a given limit value.

A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other and in a ladder configuration. The overall delay imposed on the edge after it has passed through both sub-circuits has delay contributions from both types of transistors. The delay circuit may have enhanced performance because of finer delay control granularity by providing a first circuit stage that comprises a plurality of transistors for relatively fine delay adjustment to the edge and a second circuit stage that comprises a plurality of transistors for relatively coarse delay adjustment to the edge. A combination of one or more of the transistors in the first and second circuit stages may be selected to produce numerous steps or increments of delay adjustability.

A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits each of which delays the clock signal by a desired amount so as to synchronize arrival of the clock signal when distributed to each of the plurality of points on the circuit. Each digitally programmable delay circuit comprises a plurality of circuit stages connected in series with each other. Each circuit stage comprises a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other, and a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other. In each circuit stage, one or more of the plurality of transistors of the first type are selected to delay a rising edge, and one or more of the plurality of transistors of a second type are selected to delay a falling edge.

A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other and in a ladder configuration. The overall delay imposed on the edge after it has passed through both sub-circuits has delay contributions from both types of transistors. The delay circuit may have enhanced performance because of finer delay control granularity by providing a first circuit stage that comprises a plurality of transistors for relatively fine delay adjustment to the edge and a second circuit stage that comprises a plurality of transistors for relatively coarse delay adjustment to the edge. A combination of one or more of the transistors in the first and second circuit stages may be selected to produce numerous steps or increments of delay adjustability.