One embodiment of the present invention provides a system that controls rippling caused by optical proximity correction during an optical lithography process for manufacturing an integrated circuit. During operation, the system selects an evaluation point for a given segment, wherein the given segment is located on an edge in the layout of the integrated circuit. The system also selects a supplemental evaluation point for the given segment. Next, the system computes a deviation from a target location for the given segment at the evaluation point. The system also computes a supplemental deviation at the supplemental evaluation point. Next, the system adjusts a bias for the given segment, if necessary, based upon the deviation at the evaluation point. The system also calculates a ripple for the given segment based upon the deviation at the evaluation point and the supplemental deviation at the supplemental evaluation point. If this ripple exceeds a threshold value, the system performs a ripple control operation.

A method of controlling one or more critical dimension (CD) features, dependent upon at least a first and a second processing parameter, with a single metrology step, while still enabling decoupled feedback to the first and the second processing parameter, includes an initial process characterization; producing a production piece; a single metrology step to determine the critical dimensions of the produced features; solving a system of equations simultaneously for individual feedback correction values for the first and second processing parameters; and applying the individual feedback correction values to their respective processing parameters.

Electron beam (e-beam) shot linearity monitoring is disclosed. A pattern is written that has a predetermined size and a predetermined form in a predetermined position on a substrate, such as a semiconductor wafer, a reticle, or a photomask. The pattern writing fixes the e-beam shot size, as located along one or more critical dimensions of the pattern. The critical dimensions are then measured, where their variations reflect the e-beam shot size linearity. Thereafter, deficiencies in the e-beam shot size linearity can be compensated for, to allow for properly produced semiconductor patterns.

A system, method and software product to optimize optical and/or digital system designs. An optical model of the optical system design is generated. A digital model of the digital system design is generated. Simulated output of the optical and digital models is analyzed to produce a score. The score is processed to determine whether the simulated output achieves one or more goals. One or more properties of at least one of the optical model and the digital model is modified if the goals are not achieved. The analyzing, processing and modifying is repeated until the goals are achieved, and an optimized optical system design and optimized digital system design are generated from the optical and digital models.

There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.