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Diagnosis of RAMS using functional patterns    
United States Patent6519725   
Link to this pagehttp://www.wikipatents.com/6519725.html
Inventor(s)Huisman; Leendert M. (South Burlington, VT); Lai; Ya-Chieh (Ibaraki, JP)
AbstractA methodology for testing embedded memories based on functional patterns that allow for easy and complete diagnosis including techniques for shortening the size of the array test, and/or the simulation turn around time, without diminishing the diagnostic accuracy.



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Patent Text Patent PDF Print Page Summary File History
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Inventor     Huisman; Leendert M. (South Burlington, VT); Lai; Ya-Chieh (Ibaraki, JP)
Owner/Assignee     International Business Machines Corporation (Armonk, NY)
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Publication Date     February 11, 2003
Application Number     08/811,605
PAIR File History     Application Data   Transaction History
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Litigation
Filing Date     March 4, 1997
US Classification    
Int'l Classification    
Examiner     Decady; Albert
Assistant Examiner     Lamarre; Guy
Attorney/Law Firm     Shikurko; Eugene I. Chadurjian; Mark F.
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Patent Tags     diagnosis rams functional patterns
   
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5471482
Byers
714/719
Nov,1995

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5436910
Takeshima
714/718
Jul,1995

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Valentaten
345/541
Oct,1993

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Polstra
714/29
Aug,1992

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Obermeyer
714/718
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Kuo

Jul,1991

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What is claimed is:

1. A method comprising the steps of: a) exercising an embedded memory, including writing to at least a plurality of memory locations in the embedded memory test data followed by reading data from said at least a plurality of memory locations, said writing and reading steps each including a plurality of operations; b) simulating the exercising step to generate expected test read data; c) comparing the data read from the embedded memory with the expected test read data; d) providing miscompare data at each occurrence of a miscompare during the comparing step, the miscompare data including at least one location address of said at least a plurality of memory locations corresponding to the miscompare and an operation of a writing step that wrote test data to said at least one location address of said at least a plurality of memory locations corresponding to the miscompare; and e) diagnosing a cause of the miscompare including correlating the miscompare data with known fault signatures.

2. The method according to claim 1, wherein the providing step includes storing the miscompare data in a buffer.

3. The method according to claim 2, wherein the exercising step continues uninterrupted while the providing step provides and stores the miscompare data.

4. The method according to claim 1, wherein said correlating the miscompare data with known fault signatures includes selecting said cause from a set of known causes.

5. The method according to claim 1, wherein said exercising step further includes executing a verification program containing the test data on a processor containing the embedded memory.

6. The method according to claim 5, wherein said executing step includes loading the verification program into the processor through input pins of an IC chip containing the processor.

7. In a method for testing RAM, the method including a plurality of operations each including writing to and reading from data locations in the RAM, and comparing data read from said data locations in the RAM with expected data values, the improvement comprising the steps of: providing an address of a RAM location whose data miscompared with one of said expected data values; and providing operation information that identifies which of said plurality of operations resulted in a miscompare.

8. The improvement of claim 7 further comprising the step of storing the address of the RAM location and the operation information in a fail buffer.

9. The improvement of claim 8 further comprising the step of diagnosing a cause of the miscompare including correlating the operation information with known fault signatures.

10. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for testing and diagnosing memory failures, said method steps comprising: a) exercising an embedded memory, including writing to at least a plurality of memory locations in the embedded memory test data followed by reading data from said at least a plurality of memory locations, said writing and reading steps each including a plurality of operations; b) simulating the exercising step to generate expected test read data; c) comparing the data read from the embedded memory with the expected test read data; d) providing miscompare data at each occurrence of a miscompare during the comparing step, the miscompare data including at least one location address of said at least a plurality of memory locations corresponding to the miscompare and an operation of a writing step that wrote test data to said at least one location address of said at least a plurality of memory locations corresponding to the miscompare; and e) diagnosing a cause of the miscompare including correlating the miscompare data with known fault signatures.

11. The method according to claim 10, wherein the providing step includes storing the miscompare data in a buffer.

12. The method according to claim 11, wherein the exercising step continues uninterrupted while the providing step provides and stores the miscompare data.

13. The method according to claim 10, wherein said correlating the miscompare data with known fault signatures includes selecting said cause from a set of known causes.

14. The method according to claim 10, wherein said exercising step further includes executing a verification program containing the test data on a processor containing the embedded memory.

15. The method according to claim 14, wherein said executing step includes loading the verification program into the processor through input pins of an IC chip containing the processor.
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