Provided is a digital duty cycle corrector capable of generating a clock signal with the rate of duty 50:50, by means of three or more duty cycle correction circuits assigning different weight values to first and second clock signals that are different in duty cycle each other in order to reduce a phase difference between the first and second clock signals, and one or more duty cycle correction circuits assigning the same weight value to the first and second clock signals in order to eliminate a phase difference between the first and second clock signals.

Digital duty cycle correction circuits are provided including a duty cycle detector circuit configured to generate first and second control values associated with a first internal clock signal and a second internal clock signal, respectively. A comparator circuit is also provided and is configured to compare the first control value to the second control value and provide a comparison result. A counter circuit is configured to perform an addition and/or a subtraction operation responsive to the comparison result to provide a digital code. A digital to analog converter is configured to generate third and fourth control values responsive to the digital code. Finally, a duty cycle corrector circuit is configured to receive first and second external clock signals and the first through fourth control values and generate the first and second internal clock signals having a corrected duty cycle. The first and second control values are received over a first path and the third and fourth control values are received over a second path, different from the first path. Related methods of operating duty cycle correction circuits are also provided.

A device for correcting the duty cycle of a clock signal with a duty cycle modifying device which receives a clock signal and a complementary clock signal, which comprises a delay device for both clock signals, and which is adapted to generate a clock signal and a complementary clock signal with corrected duty cycle. The invention also relates to a corresponding method for correcting the duty cycle of a clock signal and may preferably be used to correct the duty cycle of the system clock input in a DDR-SDRAM device in order that an ideal duty cycle of 50 percent is achieved in the memory chip during the processing thereof to a data strobe. As compared to previous similar devices and methods, the invention thus enables, with DDR-SDRAM devices, a more precise reading out of the data from the devices to the system associated with the devices.

A signal generation apparatus, a frequency converting apparatus and a receiver, in which the signal generation apparatus includes an oscillator, a duty cycle adjusting circuit, and a signal generation circuit. The oscillator generates differential signals. The duty cycle adjusting circuit adjusts duty cycles of differential output signals, in response to at least one of a plurality of control signals, to adjust phases of the differential output signals generated according to a result of amplifying a difference between the differential signals input through a pair of input terminals so as to output duty cycle adjusted differential output signals to a pair of output terminals. The signal generation circuit outputs an in-phase signal and a quadrature-phase signal in response to the duty cycle adjusted differential output signals. The frequency converting apparatus includes a first mixer for mixing an input signal with the in-phase signal and a second mixer for mixing the input signal and the quadrature-phase signal.

A clock duty ratio correction circuit corrects a duty ratio of internal clock signals at 1:1. The clock duty ratio correction circuit comprises a clock buffer unit, a charge pump unit, a comparison control unit, a voltage comparison unit, a counter and a D/A converter. The clock duty ratio correction circuit converts a differential internal clock signal into a voltage level corresponding to the pulse width of the differential internal clock signal, and compares the voltage level to generate a count signal. Additionally, the clock duty ratio correction circuit divides a reference voltage at a predetermined ratio in response to the count signal to generate a duty ratio correcting signal, and corrects the duty ratio of the differential internal clock signal by using the voltage level difference of the duty ratio correcting signal.